PCMS Refresh Logic Circuit for Memory Power Optimization
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Solution Overview
Problem
Conventional computer systems face limitations in memory and storage technologies, including high power consumption, volatility, and speed constraints in DRAM and flash memory, which hinder performance and efficiency, especially in mobile devices and systems requiring increased memory capacity and speed.
Innovation Solution
Implementing a multi-level memory hierarchy that incorporates non-volatile random access memory (NVRAM), such as Phase Change Memory (PCM), which provides lower power consumption, higher speed, and greater write endurance, allowing for a more efficient and scalable memory subsystem organization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If DRAM-based memory is used for system memory, then high speed access is achieved, but power consumption increases due to constant capacitor recharging
Solution Approach 1:
The memory system is segmented into multiple tiers: volatile DRAM for frequently accessed data requiring high speed, and non-volatile memory for less frequently accessed data. This segmentation allows each memory type to operate in its optimal performance range while reducing overall power consumption by minimizing DRAM refresh operations.
Solution Approach 2:
Instead of continuous power consumption for maintaining DRAM state, the system uses periodic refresh operations only when data is actively accessed or needs to be maintained in volatile memory. Non-volatile memory eliminates the need for periodic refresh, consuming power only during write operations.
2Stability of the object's composition
If flash memory is used for mass storage, then non-volatility is achieved, but access speed decreases due to I/O protocol overhead
Solution Approach 1:
A memory controller acts as an intermediary between the processor and non-volatile memory, implementing a transactional protocol that abstracts away the complexities of flash memory I/O operations. This intermediary layer optimizes data transfer by batching operations, managing wear-leveling, and providing a unified interface that appears as high-speed memory to the processor.
3Speed
If cache memory is used to improve performance, then access speed increases, but device complexity increases due to multiple cache levels and management protocols
Solution Approach 1:
The system merges the functions of multiple cache levels into a unified memory hierarchy managed by a single memory controller. The non-volatile memory tier provides both bulk storage and caching capabilities, eliminating the need for separate L2 and L3 caches while maintaining performance through intelligent data placement and retrieval strategies.
4Use of energy by moving object
If non-volatile memory is used for system memory, then power consumption decreases and write endurance increases, but access speed may be reduced compared to DRAM
Solution Approach 1:
Different regions of the memory system are assigned different qualities: DRAM provides locally optimized high-speed access for active working sets, while non-volatile memory provides globally optimized low-power storage for less frequently accessed data. The system dynamically determines which memory tier to use based on access patterns and data importance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved performance and capacity in memory systems by leveraging NVRAM's characteristics, such as byte-level granularity and transactional protocols, to reduce power consumption and increase write endurance, thereby enhancing overall system efficiency and flexibility.
Implementation Method 1
Phase-change memory (PCM), also sometimes referred to as phase change random access memory (PRAM or PCRAM), PCME, Ovonic Unified Memory, or Chalcogenide RAM (C-RAM), is a type of non-volatile computer memory which exploits the unique behavior of chalcogenide glass. As a result of heat produced by the passage of an electric current, chalcogenide glass can be switched between two states: crystalline and amorphous.
Data Source
AI summary
An apparatus is described having invert determination logic circuitry to determine if a read data path that transports data read from a PCMS memory device is to be inverted or not inverted as a function of whether information represented by the data was last written in an inverted or non inverted logical state to the PCMS memory device during a refresh of said PCMS memory device.