Semiconductor PCMTEG Segmentation for Probe Card Measurement Efficiency

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Solution Overview

Problem

The existing semiconductor device measurement process for PCMTEGs is inefficient, requiring long measurement times and prone to inaccurate results due to probe card movement and potential needle defects, which increases workload and risks overlooking quality defects.

Innovation Solution

A semiconductor device with a PCMTEG region divided into a main and sub-PCMTEG region, where TEGs with specifications are collectively arranged in the sub-PCMTEG region, allowing for reduced measurement time and improved productivity by minimizing probe card movement and ensuring accurate contact verification.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the probe card is moved to bring needles into contact with multiple PCMTEGs for measurement, then electrical measurements can be performed on different TEGs, but the measurement time increases and productivity decreases

Engineering Contradiction:

Improveelectrical measurement capabilityVSAvoidmeasurement time

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The PCMTEG region is divided into multiple TEG classification regions, each containing TEGs of the same type. This segmentation allows the probe card to measure all TEGs of a specific type within one region before moving to the next region, reducing the total number of movements required and thereby decreasing measurement time while maintaining measurement capability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

TEGs are pre-arranged in classification regions according to their types before measurement. This preliminary organization enables the probe card to perform measurements in an optimized sequence without requiring complex real-time decision-making about probe card movement, thus reducing measurement time and improving productivity

Inventive Principle:

Principle #10Preliminary action

2Reliability

If the probe card moves extensively to measure all PCMTEGs, then complete electrical characterization is achieved, but the workload and measurement time increase

Engineering Contradiction:

Improvequality control accuracyVSAvoidmeasurement time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

By segmenting the PCMTEG region into type-specific classification regions, the patent enables systematic measurement of all TEGs while reducing redundant probe card movements. This ensures complete electrical characterization is achieved without unnecessary time loss

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The structured arrangement of TEGs in classification regions provides a systematic measurement path that reduces the likelihood of measurement errors and enables efficient verification of all TEGs, improving reliability while reducing measurement time

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS11631620B2Semiconductor device and method of testing a semiconductor device

Publication Date: 2023.04.18 ABLIC INC

AI summary

Provided is a semiconductor device that allows reduction of a measurement time of a PCMTEG and improvement of productivity in an IC manufacturing process. A PCMTEG region 100 formed on a surface of a semiconductor substrate is divided into a main PCMTEG region 101 and a sub-PCMTEG region 102, and TEGs having specifications for their electrical characteristic values are all collectively arranged in the sub-PCMTEG region 102.