PCR Insertion During Packetization Before Buffering

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Solution Overview

Problem

Conventional video compression systems face inefficiencies in PCR insertion, particularly when packetization occurs before buffering, leading to variable bit rates and reduced bandwidth utilization, which affects the regularity and timing of Program Clock References (PCRs) in MPEG transport streams.

Innovation Solution

A method that calculates an expected time for each byte to leave the buffer and generates an insert_PCR signal to insert PCRs at precise intervals during packetization, ensuring they appear evenly spaced and at the correct rate in the output stream, even before buffering occurs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If packetization is performed before buffering, then bandwidth utilization is improved and bandwidth margins are reduced, but the regularity and timing of PCR insertion deteriorates due to variable bit rates

Engineering Contradiction:
Improvebandwidth utilizationVSAvoidPCR timing regularity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary calculation of the number of bytes to be buffered based on expected bit rates and PCR timing requirements before actual packetization. This allows the system to determine PCR insertion points in advance, ensuring regular timing even when packetization occurs before buffering. The calculation predicts buffer exit times and uses this information to schedule PCR insertions at appropriate intervals.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically adjusts PCR insertion timing based on variable bit rate conditions. Instead of using fixed time intervals, the system calculates variable byte intervals that account for changes in encoder output rates. This dynamic approach allows PCRs to be inserted at regular time intervals in the output stream even though the input packetization rate varies, resolving the contradiction between variable bit rate efficiency and PCR timing regularity.

Inventive Principle:
Principle #15Dynamics

2Reliability

If PCR is inserted at regular time intervals after buffering, then decoder synchronization is maintained, but bandwidth is wasted due to constant allocation of bandwidth margins

Engineering Contradiction:
Improvedecoder synchronizationVSAvoidbandwidth waste
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The system performs preliminary calculations to determine the exact number of bytes that will be in the buffer at any given time based on expected bit rates. This allows PCR insertions to be scheduled at precise intervals that ensure regular timing in the output stream, eliminating the need for conservative bandwidth margin allocations while maintaining synchronization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses feedback from bit rate monitoring to adjust PCR insertion timing. By continuously monitoring the actual bit rate and comparing it with expected rates, the system can adjust the number of bytes between PCRs to maintain regular timing intervals, thereby achieving reliable synchronization without wasting bandwidth on fixed margins.

Inventive Principle:
Principle #23Feedback

3Adaptability or versatility

If variable bit rates are used in statistical multiplexing, then quality loss and inefficient capacity use are avoided, but PCR insertion complexity increases due to variable timing requirements

Engineering Contradiction:
Improvebit rate allocation flexibilityVSAvoidPCR insertion control
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent calculates the number of bytes to be buffered and predicts buffer exit times in advance, before actual PCR insertion. This preliminary calculation simplifies the insertion process by providing predetermined timing information, reducing the complexity of real-time PCR insertion control in statistical multiplexing environments with variable bit rates.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the parameter used for PCR timing from fixed time intervals to variable byte intervals based on expected bit rates. This parameter transformation allows the system to maintain regular PCR timing in the output stream while accommodating variable input bit rates, simplifying the control logic by using byte counting rather than complex time-based scheduling.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10080050B2System and method for insertion of a program clock reference during packetization of an encoded data stream
Publication Date: 2018.09.18 MK SYST USA INC
  • US10080050B2 patent drawing
  • US10080050B2 patent drawing
  • US10080050B2 patent drawing

AI summary

There is provided a method for clock reference insertion during packetization of an encoded data stream, wherein said packetization is performed before buffering of the data stream. The method comprises storing the value of each bit rate applied during encoding, and the duration of time for which each bit rate is applied. A clock reference time interval is converted into a clock reference data interval using the value of each bit rate applied and the duration of time for which each bit rate is applied. The clock reference data interval is used to determine where to insert a clock reference into the data stream during packetization.