Phase Change Memory Controller Address Mapping for Write Speed
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Solution Overview
Problem
Emerging memory technologies, such as phase change random access memory (PCRAM), face challenges in matching the write speeds of traditional DRAM due to the longer time required for the 'set' operation compared to the 'reset' operation, making them unsuitable as direct replacements without modifying the host device.
Innovation Solution
Implementing a memory device with a controller that maps external memory addresses to internal memory segments, ensuring that only the faster 'reset' operation is performed during write access, and the slower 'set' operation is performed during periods of inactivity, allowing memory segments to be written to in their default, faster 'set' state initially.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If phase change memory is used to replace DRAM, then non-volatility and fast read access are achieved, but write speed is insufficient due to long set operation time
Solution Approach 1:
The memory controller pre-erases memory segments by setting all cells to the crystalline state before write operations. This preliminary action ensures that during normal write operations, only the faster reset operation is needed rather than requiring the slower set operation, thus achieving DRAM-compatible write speeds while maintaining non-volatility
2Speed
If phase change memory is used to replace DRAM, then fast read access is achieved, but write access time is too long to meet DRAM performance requirements
Solution Approach 1:
The controller performs erasure operations in advance during idle periods, preparing memory segments for future write operations. This separates the time-critical write path from the non-time-critical erasure path, allowing write operations to complete in ~10ns while erasures occur during idle time
Solution Approach 2:
The system dynamically manages memory segment states by tracking which segments are erased and ready for writing. The controller adapts its operation based on the current state of memory segments, selecting appropriate segments for write operations and scheduling erasures optimally
3Ease of operation
If all memory cells are written to during erasure, then memory segments are ready for writing, but the erasure process becomes time-consuming
Solution Approach 1:
The controller erases memory segments in advance during idle periods rather than waiting until they are needed for writing. This preliminary preparation ensures that erased segments are readily available when write operations occur, eliminating wait time without extending the critical write path
Solution Approach 2:
The system uses idle periods and refresh cycles to perform erasure operations automatically without requiring dedicated erasure time slots. This self-service approach utilizes otherwise wasted time resources to maintain a pool of ready-to-write memory segments
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables emerging memory technologies to meet the write speed requirements of traditional DRAM, allowing them to be used as drop-in replacements without modifying the host device, while optimizing the use of memory segments by performing the slower 'set' operation during less critical times.
Implementation Method 1
Phase change memory utilizes a phase change material in the resistive memory element. The phase change material exhibits at least two different states. The states of the phase change material may be referred to as the amorphous state and the crystalline state
Implementation Method 2
The reset operation may require about 10 ns to complete, which is roughly in the range of the DRAM write speed. However, the set operation may require about 50 ns to 200 ns, depending on the phase change material
Data Source
AI summary
An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address.