PCRAM Cross-Point Lattice With Common Word Lines
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Solution Overview
Problem
PCRAM devices face challenges in chip area efficiency due to large word line driver circuits and increased word line resistance, which affect overall chip performance and cost.
Innovation Solution
A novel cross-point architecture is introduced where memory cells form a centered squared lattice, reducing the number of word line driver sets and word line resistance by using common word lines and wider metal tracks, eliminating the need for costly immersion layers in the fabrication process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional cross-point architecture is used, then memory capacity can be achieved, but word line driver circuit area increases and word line resistance increases
Solution Approach 1:
The patent merges multiple word line driver circuits into a single shared driver circuit that controls multiple word lines. This is achieved by implementing a column-parallel architecture where one driver circuit can sequentially or simultaneously drive multiple word lines across different memory blocks, thereby reducing the total number of driver circuits and the area they occupy while maintaining the ability to address individual memory cells.
Solution Approach 2:
The patent implements universal word lines that can serve multiple memory blocks and functions. The word line structure is designed to be multi-functional, allowing the same word line to be used for different memory blocks (e.g., first memory block, second memory block) and for different operations (read, write, erase), thereby reducing the need for dedicated driver circuits for each function or block.
2Quantity of substance
If conventional cross-point architecture is used, then memory capacity can be achieved, but word line resistance increases affecting write current
Solution Approach 1:
The patent merges multiple memory blocks into a unified architecture where word lines are shared across blocks. This merging approach allows for wider word line metal tracks that can be formed as continuous structures spanning multiple blocks, thereby reducing resistance and improving write current delivery to any specific memory cell within the expanded memory capacity.
Solution Approach 2:
The patent transitions from a two-dimensional word line layout to a three-dimensional structure by forming word lines that extend across multiple memory blocks in the horizontal direction and utilizing vertical stacking for memory cells. This dimensional change allows for wider metal tracks with lower resistance while maintaining high memory density through vertical arrangement of memory cells above the shared word lines.
3Ease of manufacture
If conventional cross-point architecture is used, then standard fabrication can be used, but immersion layers increase cost
Solution Approach 1:
The patent extracts and eliminates the requirement for immersion layers from the fabrication process by redesigning the word line metal track formation process. Instead of using immersion lithography to create narrow, precise patterns, the invention uses conventional lithography with adjusted design rules that accommodate wider metal tracks, thereby removing the need for costly immersion layers while maintaining manufacturability.
Solution Approach 2:
The patent replaces expensive immersion layer materials and processes with conventional, cheaper lithography materials and processes. By accepting wider metal track dimensions that can be formed with standard lithography, the invention substitutes costly specialized materials (immersion layers) with常规 materials that are part of standard fabrication processes, reducing overall device cost.
Data Source
AI summary
A cell array of a memory device includes: a first deck of memory cells arranged in a first row and a second row and a plurality of columns, wherein the memory cells in the second row in the first deck is displaced in the first horizontal direction with respect to the memory cells in the first row in the first deck; a first common word line metal track; and a plurality of first bit line metal tracks, wherein the plurality of first bit line metal tracks comprises a first group of first bit line metal tracks and a second group of first bit line metal tracks interposed in the first horizontal direction, and each of the first group is disposed on only one of the memory cells in the first row, and each of the second group is disposed on only one of the memory cells in the second row.