Multi-level Programmable PCRAM Memory with Phase Change Layers
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Solution Overview
Problem
Non-volatile memory devices face reliability issues due to dielectric defects and scaling challenges, which affect current carrier flow and programming efficiency, particularly as semiconductor devices shrink in size, leading to increased power consumption and reduced performance.
Innovation Solution
The use of phase change materials, such as germanium antimony tellurium (Ge2Sb2Te5), in multi-layer configurations with varying melting points and glass transition temperatures, allows for the creation of multiple resistance states by controlling the amorphous and crystalline phases, enabling more programmable logic states and improved scalability without the limitations of traditional transistor-based memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dielectric layer thickness is reduced to enable rapid current flow, then current flow speed is improved, but dielectric reliability deteriorates due to increased defect sensitivity
Solution Approach 1:
The patent divides the memory cell structure into multiple independent phase change material layers separated by conductive layers, replacing the traditional single dielectric layer approach. This segmentation allows each layer to be independently controlled and read, enabling multi-level storage while maintaining reliability through redundancy
Solution Approach 2:
The patent uses composite phase change material structures combining different materials with distinct melting points and glass transition temperatures (e.g., GST layers with oxygen doping). This composite approach enables precise control over electrical resistance states while maintaining structural stability and reliability
2Use of energy by moving object
If transistor size is reduced to decrease power consumption, then power consumption is reduced, but dielectric quality and reliability worsen
Solution Approach 1:
The patent replaces the traditional transistor-based switching mechanism with a diode-based selection mechanism combined with phase change material resistance switching. This substitution eliminates the need for complex transistor gate dielectrics, enabling extreme miniaturization while maintaining reliability through the inherent stability of phase change materials
Solution Approach 2:
The patent exploits changes in electrical resistance parameter of phase change materials through phase transitions (crystalline to amorphous). By controlling the resistance states of multiple phase change layers, the system achieves multi-level storage functionality without requiring proportional reduction in device dimensions, thus maintaining reliability while reducing power consumption
3Adaptability or versatility
If phase change material layers are used to create multiple resistance states, then programmable logic states are improved, but device complexity increases
Solution Approach 1:
The patent merges multiple phase change material layers and conductive layers into a single integrated memory cell structure. By combining the functionality of multiple resistance switching elements in series, the system achieves multi-level storage capability while using a unified fabrication process, thereby reducing overall device complexity despite increased programmable states
Solution Approach 2:
The patent designs the phase change material layers to serve multiple functions simultaneously: data storage, data retention, and selective addressing. Each layer can be independently programmed to different resistance states and read without affecting other layers, providing universal functionality that reduces the need for additional control circuitry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of reliable, scalable non-volatile memory devices with multiple discrete resistance states, reducing the number of memory cells required for data storage and enhancing reliability and performance by leveraging the distinct electrical resistances of phase change materials in amorphous and crystalline states.
Implementation Method 1
Phase change materials have a different electrical resistance in a polycrystalline phase as compared to an electrical resistance in an amorphous phase, and such phase change materials may be changed from a crystalline state (equivalent to an on state, for example a 1 state) to an amorphous state (equivalent to an off state, for example a 0 state)
Implementation Method 2
applying a set current having a set current level selected to raise a temperature of the memory to a level that is below a melting temperature, but above a glass transition temperature, of every phase change material layer
Data Source
AI summary
A series of phase change material layers sandwiched between a bottom electrode and a top electrode may have different phase change temperatures selected to provide a memory device having three or more discrete resistance levels, and thus three or more discrete logic levels. The non-volatile memory device may be formed with diodes providing the thermal energy for the phase changes that program the device logic level. The non-volatile memory may form part of a logic device and/or a memory array device, as well as other devices and systems. The phase change material layers may be formed using physical deposition methods, chemical deposition methods, or using atomic layer deposition. Atomic layer deposition may reduce the overall device thermal exposure and provide improved layer thickness uniformity and sharp material boundaries at the interface of different phase change materials, thus providing improved resistance level accuracy.