PCRAM Sensing Reference Voltage Adjustment for Resistance Drift
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Solution Overview
Problem
In phase change random access memory (PCRAM) circuits, the resistance drift of variable resistors like GST leads to inaccurate data determination during verify read operations, especially when performed early, resulting in incorrect data verification and unnecessary write operations due to the unstable amorphous state.
Innovation Solution
A non-volatile semiconductor memory circuit with a control signal generation unit and sensing block that provides different sensing reference voltages for normal and verify read operations, using a verification sensing reference voltage set based on the timing of the verify read operation to compensate for resistance drift, allowing for accurate data verification and reduced write times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a verify read operation is performed at an earlier timing during write operation, then write time is reduced, but data determination accuracy deteriorates due to resistance drift in the amorphous state
Solution Approach 1:
The patent changes the sensing reference voltage parameter based on the operation type. During verify read operations, a first sensing reference voltage (lower level) is applied, while during normal read operations, a second sensing reference voltage (higher level) is applied. This parameter change compensates for resistance drift in the amorphous state, enabling accurate data determination even when verify read is performed at earlier timing during write operations.
2Measurement precision
If a higher sensing reference voltage is used during verify read operation, then data determination accuracy improves, but the amorphous state resistance drift causes incorrect verification
Solution Approach 1:
The patent applies a lower first sensing reference voltage during verify read operations to match the lower resistance state of the amorphous phase change material at early verification timing. This prevents incorrect verification that would occur with a higher reference voltage, thereby improving both measurement precision and reliability.
3Reliability
If multiple write operations are performed due to incorrect verification, then data accuracy improves, but write time increases and PCRAM cells undergo aging
Solution Approach 1:
By changing the sensing reference voltage to a lower level during verify read operations, the patent enables correct data determination in the first verification attempt. This eliminates the need for multiple corrective write operations, thereby improving data accuracy while reducing total write time and minimizing PCRAM cell aging from repeated write pulses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces determination errors and write times by using a lower sensing reference voltage during verify read operations, preventing unnecessary write pulses and protecting PCRAM cells from aging.
Implementation Method 1
The amorphous state of the variable resistor GST exhibits an intrinsic kinetic physical characteristic which is thought to be brought about by relatively slow solid state reorganization mechanisms that are driven by the diffusion of the excess imposed Joule heat.
Implementation Method 2
The PCRAM can store data in a memory cell by controlling a reversible phase change of the variable resistor GST using an electric pulse.
Implementation Method 3
The resistance drift refers to a phenomenon in which the resistance of the variable resistor GST increases with time due to various causes.
Data Source
AI summary
A non-volatile semiconductor memory circuit for use in compensating for time dependent resistive changes in phase change memory cells is presented. The non-volatile semiconductor memory circuit includes a control signal generation unit and a sensing block. The control signal generation unit is configured to provide a control signal having a voltage level corresponding to a read command or a write command. The sensing block is configured to selectively provide a first sensing reference voltage substantially equal to a reference voltage. The sensing block is also configured to selectively provide a second sensing reference voltage which is lower than the reference voltage. The first and second sensing reference voltages are selectively provided as a function of the voltage level of the control signal in which the first and second sensing reference voltages are used to read data of the memory cell array.