PCS Bit Interleaving for Longer-Distance QAM Transmission
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Solution Overview
Problem
Existing data processing and transmission methods using conventional QAM modulation are not applicable to future scenarios involving probabilistic constellation shaping (PCS) technology, necessitating a solution that combines FEC encoding with PCS to enhance transmission distance and performance.
Innovation Solution
A data processing method that performs PCS processing on a bit set, followed by FEC encoding interleaving, and symbol mapping to ensure equiprobable sign bits and non-equiprobable amplitude bits, using a new interleaver to maintain compatibility with existing OFEC encoding and interleavers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional QAM modulation is used with existing OFEC encoding, then the system is simple to implement, but it cannot achieve longer transmission distances and is not applicable to PCS technology
Solution Approach 1:
The patent segments the k information bits into two parts: first bit set (m bits) for PCS processing and second bit set (k-m bits) for FEC encoding. This segmentation allows independent optimization of each processing stage, enabling PCS technology integration while maintaining manageable system complexity through modular data flow management.
Solution Approach 2:
The patent introduces a new interleaver as an intermediary component between FEC encoding and symbol mapping. This intermediary reorders the encoded bits so that non-equiprobable amplitude bits are properly positioned for PCS-compatible modulation, resolving the incompatibility between existing OFEC and PCS technology without requiring complete system redesign.
2Reliability
If PCS processing is introduced to enable longer transmission, then transmission performance improves, but the overall data processing operation becomes more complex
Solution Approach 1:
The patent performs PCS processing on the first bit set before FEC encoding on the second bit set. This preliminary PCS processing prepares the amplitude bits with appropriate probability distribution in advance, allowing subsequent FEC encoding and interleaving to proceed with standard operations, thereby managing complexity through staged processing rather than simultaneous complex operations.
Solution Approach 2:
The patent applies different processing qualities to different parts of the data: the first bit set undergoes PCS processing to achieve non-uniform probability distribution for improved transmission distance, while the second bit set undergoes standard FEC encoding. This local differentiation optimizes each segment for its specific function, achieving long-distance transmission without uniformly increasing complexity across the entire system.
3Adaptability or versatility
If a new interleaver is introduced to make amplitude bits non-equiprobable for PCS, then compatibility with PCS is achieved, but the existing OFEC encoding structure is impacted
Solution Approach 1:
The patent implements a dynamic interleaving structure that adapts to PCS requirements. The interleaver dynamically reorders bits based on their function (amplitude vs. phase bits), creating a flexible mapping that achieves PCS compatibility. This dynamic approach allows the system to maintain OFEC encoding benefits while adapting to PCS modulation requirements without rigid structural changes.
Solution Approach 2:
The new interleaver is designed to perform multiple functions: it reorders bits for PCS compatibility, maintains FEC encoding integrity, and prepares data for symbol mapping. This multi-functional interleaver reduces the need for separate dedicated components, achieving PCS adaptability while managing overall system complexity through consolidated functionality.
Data Source
AI summary
In an example method, probabilistic constellation shaping (PCS) processing is performed on a first bit set in k bits, to obtain a second bit set. Forward error correction (FEC) encoding is performed on the second bit set and a third bit set in the k bits excluding the first bit set, to obtain a fourth bit set. The fourth bit set includes m0 first bit subsets, and each of the first bit subsets includes F0 bits. First interleaving processing is performed on the fourth bit set to obtain a fifth bit set. The fifth bit set includes m0 second bit subsets, each of the second bit subsets includes F0 bits, F0/2 bits in each of the second bit subsets are from the second bit set, and the other F0/2 bits in each of the second bit subsets are from the third bit set and/or parity bits of the FEC encoding.