Modified PCS Bit Ordering for FEC Burst Resiliency
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Solution Overview
Problem
The Ethernet Physical Coding Sublayer (PCS) functional block's performance is degraded when bit-multiplexing is applied, especially at high data rates like 800 Gb/s over four physical lanes, due to the Reed-Solomon Forward Error Correction (RS-FEC) code's inability to effectively correct burst errors caused by bit-multiplexing.
Innovation Solution
The implementation of modified PCS bit ordering techniques that re-order bits to optimize the performance of the FEC decoder, specifically by rearranging bits such that each physical lane receives a sequence of groups of bits from one FEC codeword followed by another, minimizing the impact of error bursts and improving FEC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bit-multiplexing is applied to increase data rate, then productivity is improved, but reliability deteriorates due to increased error burst impact on FEC decoding
Solution Approach 1:
The patent segments the bit stream into multiple lanes and applies different bit ordering patterns to each lane. This segmentation allows the system to maintain high data rates through multiplexing while protecting against error bursts by ensuring that errors in one lane do not propagate to affect the same position in other lanes, thus preserving FEC decoding performance
Solution Approach 2:
The patent introduces a new dimension of bit ordering optimization by applying specific permutation patterns across lanes. Instead of simply increasing data rate through multiplexing, the patent adds a dimensional transformation layer that reorders bits in a way that distributes error burst impact across different spatial dimensions (lanes), thereby maintaining reliability while achieving high productivity
2Productivity
If higher muxing ratio is used to achieve 800 Gb/s, then productivity is improved, but reliability deteriorates with unacceptable FEC performance degradation
Solution Approach 1:
The patent applies local quality optimization by implementing lane-specific bit ordering patterns. Each lane receives a customized bit ordering that is optimized for its position in the multiplexed structure. This local optimization ensures that even at high muxing ratios like 8:1, the FEC decoding performance is preserved by tailoring the bit distribution to minimize error burst impact at each specific lane location
3Reliability
If modified bit ordering is applied to improve FEC performance, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent changes the parameter of bit ordering pattern from the standard pattern to an optimized pattern. By modifying this single parameter (the bit ordering sequence) rather than the overall system architecture, the patent achieves improved FEC decoding performance while minimizing the increase in device complexity. The change is localized to the bit ordering logic within the PCS functional block
Data Source
AI summary
Techniques are provided to provide modified bit sequences generated by the Physical Coding Sublayer (PCS) functional block in a way that considers the subsequent bit-mux operation of the Physical Media Attachment (PMA) sublayer functional block, in order to create symbol sequences for transmission over the physical channels with properties that optimize the performance of the Forward Error Correction (FEC) decoder with error bursts.