PCS Clock Synchronization Using 130-Bit Block Boundary Detection
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Solution Overview
Problem
The conventional Physical Coding Sublayer (PCS) architecture in the Peripheral Component Interconnect Express (PCIe) standard is complex and does not provide a clear solution for handling the 130 bit block boundary when variable length skip (SKP) ordered sets are involved, leading to difficulties in data transmission across links with different clock speeds.
Innovation Solution
The improved PCS architecture includes an encoder circuit that appends headers to data blocks, a block synchronization circuit that identifies and signals block boundaries, a decoder circuit that removes headers, and a bandwidth balance buffer that compensates for clock differences, enabling efficient data transmission and reception across links with varying bit rates by converting between 128b and 130b formats and managing SKP ordered sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the conventional PCS architecture is used, then data transmission can be performed, but the architecture becomes complex and cannot clearly handle block boundaries with variable length SKP ordered sets
Solution Approach 1:
The patent segments the data stream into fixed 130-bit blocks by inserting synchronization headers (01 followed by 128 bits of data) at clearly defined boundaries. This segmentation approach allows the block synchronization circuit to easily identify block boundaries through the unique synchronization pattern, resolving the complexity of handling variable length SKP ordered sets while maintaining reliable block boundary detection.
2Adaptability or versatility
If variable length SKP ordered sets are used to compensate for clock differences, then data transmission across different clock speeds is enabled, but the block boundary identification becomes ambiguous
Solution Approach 1:
The block synchronization circuit uses feedback mechanisms to continuously monitor the data stream for synchronization headers (01 pattern). When a synchronization header is detected, the circuit confirms block boundary alignment and adjusts its state accordingly. This feedback-based approach enables reliable block boundary detection even in the presence of variable length SKP ordered sets, as the synchronization pattern provides continuous verification of boundary positions.
3Reliability
If a complex PCS architecture is implemented to handle all edge cases, then comprehensive coverage is achieved, but the implementation becomes difficult and error-prone
Solution Approach 1:
The patent extracts the block boundary identification function into a dedicated block synchronization circuit that operates independently from the main data path. This circuit specifically searches for and identifies synchronization headers (01 pattern) to mark block boundaries, separating this critical function from the complex variable length SKP ordered set handling. This extraction simplifies the overall implementation by creating a focused, reliable boundary detection mechanism that can be implemented with simpler logic.
Data Source
AI summary
A physical coding sublayer includes a first channel configured to receive a first encoded data stream from a physical media attachment layer and to provide a first decoded data stream to a media access layer. The first channel includes a first circuit configured to detect synchronization headers in the first encoded data stream received from the physical media attachment layer, a decoding circuit configured to decode the encoded data stream and to adjust a width of the received data from a first width to a second width based on a signal identifying the synchronization headers received from the first circuit, and a first single configured to compensate for clock differences between the physical media attachment layer and the media access layer to which the first buffer provides the first decoded data stream.