Configurable PCS and FEC Circuit for Multi-Rate Ethernet

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Solution Overview

Problem

Current communication systems face challenges in supporting multiple Ethernet standards on a single device, requiring separate components and configurations for different data rates, which increases design complexity and resource utilization.

Innovation Solution

A method and system utilizing programmable logic devices (PLDs) like FPGAs to configure communication circuits to support multiple Ethernet standards by employing Physical Coding Sublayer (PCS) modules and Forward Error Correction (FEC) encoding/decoding modules, allowing data transmission at various rates such as 10 GbE and 40 GbE, and enabling devices to communicate over a single communication link.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate components and configurations are used for different data rates, then multiple Ethernet standards can be supported, but design complexity and resource utilization increase

Engineering Contradiction:
Improvesupport for multiple Ethernet standardsVSAvoiddesign complexity and resource utilization
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal communication circuit that can operate at multiple data rates (10GbE, 40GbE, and future standards) by using configurable PCS modules and FEC encoding/decoding modules. The circuit uses a common channel structure that can be dynamically reconfigured through control signals to support different Ethernet standards, eliminating the need for separate dedicated circuits for each standard.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The communication circuit employs dynamic reconfiguration capabilities where the PCS module and FEC modules can be programmatically adjusted to operate at different data rates. Control logic dynamically configures the channel parameters, encoding schemes, and transmission rates based on the detected Ethernet standard, allowing the same hardware to adapt its behavior for different standards without physical reconfiguration.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If a single device supports multiple communication standards, then resource utilization improves, but the configuration and operation complexity increases

Engineering Contradiction:
Improveresource utilization efficiencyVSAvoidconfiguration and operation simplicity
Core Design Contradiction:
Device complexityVSEase of operation

Solution Approach 1:

The communication circuit incorporates automatic detection and configuration capabilities that allow it to self-identify the required Ethernet standard and automatically adjust its operating parameters. The system performs autonomous negotiation with connected devices to determine the appropriate data rate and standard, eliminating the need for manual configuration by users or system administrators.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The system implements feedback mechanisms where the communication circuit continuously monitors the operational status, error rates, and performance metrics of the active connection. Based on this feedback, the control logic automatically adjusts configuration parameters to optimize performance for the current Ethernet standard being used, simplifying operation while maintaining efficiency.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8984380B2Method and system for operating a communication circuit configurable to support one or more data rates
Publication Date: 2015.03.17 ALTERA CORP
  • US8984380B2 patent drawing
  • US8984380B2 patent drawing
  • US8984380B2 patent drawing

AI summary

A method and system for operating a communication circuit that is configurable to support one or more communication standards on a single device. The communication circuit includes a transmitting device that comprises a PCS module operating at a first data rate, and a second PCS module operating at a second data rate. The circuit also includes a plurality of forward error correction (FEC) encoding and decoding modules, each operating at a specified data rate. A first group of FEC encoding and decoding modules is configured to support the first PCS module, and a second group of FEC encoding and decoding modules is configured to support the second PCS module.