Physical Coding Sublayer Latency Reduction via Fixed Ratio Clock Synchronization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High latency in Ethernet systems with multiple clock domains, particularly in 40G and 100G Ethernet implementations, due to data reformattings and clock boundary crossings, which are exacerbated by the complexity of these systems compared to 10G Ethernet.
Innovation Solution
Implementing a computer program product that utilizes a fixed ratio between the MAC sublayer clock frequency and the PMA clock frequency, eliminating the need for large data buffers by synchronizing data transmission directly between these domains without buffering, and optimizing the receive PCS structure to reduce latency through plesiochronous FIFOs and reduced asynchronous clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted between multiple clock domains in standard Ethernet implementations, then data can be processed through different stages (MAC sublayer to PCS Core), but latency increases to 400-500 ns due to buffering requirements
Solution Approach 1:
The patent extracts and removes the buffering stage from the data transmission path between clock domains. By eliminating the buffer that causes 400-500 ns latency, the system achieves direct data transmission from MAC sublayer to PCS Core with reduced latency of approximately 60 ns, while maintaining data integrity through fixed ratio clock synchronization.
2Reliability
If large data buffers are used to synchronize data between clock domains, then data transmission reliability is maintained, but device complexity and latency increase
Solution Approach 1:
The patent removes the large data buffer from the system by implementing direct clock domain crossing using fixed ratio synchronization. This extraction eliminates the complexity associated with buffer management, pointers, and control logic while maintaining reliable data transmission through deterministic timing relationships between clock domains.
Solution Approach 2:
The patent introduces a fixed ratio clock relationship as an intermediary mechanism between clock domains. Instead of using buffers to mediate data transfer, the system uses the fixed ratio clock synchronization as a mediator that ensures reliable data transmission without requiring complex buffering infrastructure.
3Adaptability or versatility
If multiple data reformattings are performed in the PCS, then data can be adapted for different transmission formats, but latency increases due to additional processing steps
Solution Approach 1:
The patent performs data reformatting operations in advance within the MAC sublayer before data enters the PCS Core. By completing format conversions and preparations beforehand, the system eliminates the need for additional reformatting steps in the PCS, thereby reducing processing latency while maintaining full adaptability to different data formats.
Data Source
AI summary
A system for reducing latency in a networking application includes a first clock domain operating at a first clock frequency, where a media access control (MAC) sublayer sends data to a physical coding sublayer (PCS) utilizing the first clock domain. The system also includes a second clock domain operating at a second clock frequency, where data is transmitted on one or more physical medium attachment (PMA) lanes utilizing the second clock domain, and where the first clock frequency and the second clock frequency have a fixed ratio. Data is transmitted from the first clock domain to the second clock domain without buffering the data.