SERDES Data Link Interface for Low-Latency PCS-PMA Clock Crossing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SERDES applications introduce unacceptable latency due to the use of FIFO memory to cross clock domain boundaries between Physical Coding Sublayer (PCS) and Physical Medium Attachment Sublayer (PMA) circuit blocks, which is a challenge in high-speed data transfer.
Innovation Solution
A low latency transmitter path is implemented using a data link interface that includes a programmable delay chain and a phase interpolator, coupled with a latency detector, to dynamically adjust clock signals and phase offsets, eliminating the need for FIFO memory by directly coupling the PCS and PMA circuit blocks across clock domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FIFO memory is used to cross clock domain boundaries between PCS and PMA circuit blocks, then clock skew accommodation is achieved, but data path latency becomes unacceptable
Solution Approach 1:
The patent removes the FIFO memory component from the data path entirely. Instead of using FIFO to cross clock domains, the invention directly couples the PCS and PMA circuit blocks, eliminating the latency introduced by FIFO while maintaining clock skew accommodation through direct timing control between the two clock domains
Solution Approach 2:
The patent introduces timing control mechanisms that act as intermediaries to manage the direct coupling between PCS and PMA circuit blocks. These timing controls ensure proper clock skew accommodation without requiring FIFO memory, thereby reducing data path latency while maintaining reliable clock domain crossing
2Loss of time
If direct coupling between PCS and PMA circuit blocks is implemented, then data path latency is reduced, but clock domain crossing complexity increases
Solution Approach 1:
The patent segments the clock domain crossing control into separate timing control mechanisms for the PCS and PMA circuit blocks. This segmentation allows independent control of each block's timing, simplifying the overall complexity while enabling direct coupling with reduced latency
Solution Approach 2:
The patent implements dynamic timing control that adapts to clock skew variations between the PCS and PMA clock domains. This dynamic adjustment capability allows the system to maintain reliable operation across varying conditions without requiring complex static synchronization mechanisms
Data Source
AI summary
A data link interface can include a programmable delay chain configured to provide an amount of delay to a first clock signal that clocks a first portion of a data path. The data link interface can include a phase interpolator configured to determine an amount of phase offset applied to a second clock signal that clocks a second portion of the data path. The data link interface further can include a latency detector coupled to the programmable delay chain and the phase interpolator. The latency detector can measure a phase difference between the first and second clock signals and vary the amount of delay applied to the first clock signal and/or the amount of phase offset on the second clock signal responsive to the phase difference.