PCS Frame Validity Checks to Prevent False Packet Acceptance

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Solution Overview

Problem

Existing network systems fail to reliably detect errors in Ethernet packets during transmission, leading to false packet acceptance, which reduces the Mean Time to False Packet Acceptance (MTTFPA) below the target value, affecting network performance.

Innovation Solution

Incorporating an additional length value or error detection code value into the transmission frame, computed by the transmitter and checked by the receiver, to verify the integrity of Ethernet packets encoded using 64B/66B line code, thereby enhancing error detection and reducing false packet acceptance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If standard error checking is used at the receiving network device, then the device complexity is low, but the reliability is insufficient leading to false packet acceptance

Engineering Contradiction:
Improveerror detection capabilityVSAvoiderror checking mechanism
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The transmitter performs preliminary error detection by computing a validity value (such as CRC or length check) and inserts it into the transmission frame before sending. This allows the receiver to simply compare the received validity value with a recomputed value, rather than performing complex error detection itself, thus improving reliability while keeping receiver complexity low.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The validity value acts as an intermediary that carries error detection information from the transmitter to the receiver. Instead of the receiver directly performing complex error detection on the entire packet, it uses the pre-computed validity value as a mediator to quickly determine packet integrity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If additional length value or error detection code is inserted into the transmission frame, then the reliability increases, but the device complexity increases

Engineering Contradiction:
Improvefalse packet acceptance controlVSAvoidtransmission frame processing
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error detection function is extracted from the main data payload and placed into separate dedicated fields (validity value field, length field) within the transmission frame structure. This separation allows the receiver to check error detection codes independently from processing the actual data, reducing overall processing complexity despite adding validation capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The transmission frame is segmented into distinct functional areas: data fields, control fields, and validity value fields. This segmentation allows the receiver to process different parts of the frame differently - quickly validating the integrity portion separately from the data portion, thereby managing complexity more effectively.

Inventive Principle:
Principle #1Segmentation

3Reliability

If validity value computation and insertion is performed at the transmitter, then the reliability improves, but the productivity decreases due to additional processing

Engineering Contradiction:
Improvepacket integrity verificationVSAvoiddata transmission rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The validity value computation is performed using dedicated hardware circuits (such as CRC generators or length check logic) at the transmitter, replacing software-based computation. This hardware implementation significantly reduces the time overhead for error detection, minimizing the impact on transmission productivity while maintaining high reliability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10256944B1Controlling false packet acceptance
Publication Date: 2019.04.09 MARVELL ASIA PTE LTD
  • US10256944B1 patent drawing
  • US10256944B1 patent drawing
  • US10256944B1 patent drawing

AI summary

A device includes a network interface that includes a physical coding sublayer (PCS) unit. The PCS unit receives an Ethernet packet. The PCS unit encode the Ethernet packet into a transmission frame that includes a first set of bit fields corresponding to contents of the Ethernet packet and a second set of bit fields corresponding to control information for the encoding. The PCS unit computes a validity value of the transmission frame, wherein the validity value is based on the first set of bit fields included in the transmission frame. The PCS unit inserts the validity value of the transmission frame into one or more idle bit fields in the second set of bit fields included in the transmission frame. The PCS unit processes the transmission frame for sending to a receiving device over a physical medium.