Power Control Unit for Processor Core Frequency Scaling

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Solution Overview

Problem

Current processor designs face challenges in managing power consumption effectively, as the operating system (OS) lacks understanding of workload dynamics and associated power costs, reacts slowly to hardware conditions, and fails to control performance power states per core, with turbo mode only considering thermal feedback and not core performance requirements.

Innovation Solution

The implementation of a Power Control Unit (PCU) that utilizes architectural events, monitored through EMON counters, to make informed power management decisions by scaling core frequencies based on thermal and performance feedback, enabling intelligent power management and optimization.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multi-core architecture is adopted to ease power consumption pressure, then power distribution capability is improved, but total power consumption increases linearly with the number of cores

Engineering Contradiction:

Improvepower distribution capabilityVSAvoidtotal power consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

The patent segments power management into per-core control units, allowing independent monitoring and adjustment of power states for each core based on its specific workload and performance requirements, rather than managing all cores uniformly

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically changes power state parameters (frequency, voltage, performance level) for individual cores based on real-time architectural event feedback, enabling adaptive power optimization that responds to actual hardware conditions and workload characteristics

Inventive Principle:

Principle #35Parameter changes

2Ease of operation

If OS controls power management, then power policy enforcement is improved, but response speed to hardware conditions deteriorates due to slow OS reaction

Engineering Contradiction:

Improvepower policy enforcementVSAvoidresponse speed to hardware conditions

Core Design Contradiction:

Ease of operationVSSpeed

Solution Approach 1:

The patent introduces an intermediary power management mechanism that sits between the OS and hardware, capturing architectural events directly from hardware and enabling faster response to performance and power state changes without requiring constant OS intervention

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs preliminary power management actions by monitoring architectural events and proactively adjusting power states before the OS would normally respond, enabling faster reaction to changing hardware conditions and workload demands

Inventive Principle:

Principle #10Preliminary action

3Temperature

If turbo mode uses only thermal and sensor feedback, then thermal management is improved, but performance optimization deteriorates by ignoring core performance requirements

Engineering Contradiction:

Improvethermal managementVSAvoidperformance optimization

Core Design Contradiction:

TemperatureVSProductivity

Solution Approach 1:

The patent implements a comprehensive feedback mechanism that combines thermal sensor feedback with architectural event feedback, allowing the system to make informed power management decisions that consider both thermal conditions and actual core performance requirements

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system dynamically adjusts performance parameters (frequency, power state) based on combined thermal and performance feedback, enabling turbo mode to optimize both thermal management and performance by responding to actual workload characteristics and hardware conditions

Inventive Principle:

Principle #35Parameter changes

4Loss of information

If OS monitors workload running in hardware, then power cost understanding is improved, but system complexity increases and reaction remains slow

Engineering Contradiction:

Improvepower cost understandingVSAvoidsystem complexity

Core Design Contradiction:

Loss of informationVSDevice complexity

Solution Approach 1:

The patent enables the hardware to self-monitor its own architectural events and power state through dedicated monitoring units that capture performance and power information directly from hardware components, eliminating the need for complex OS-level monitoring while providing accurate real-time feedback

Inventive Principle:

Principle #25Self-service

Data Source

PatentUS11144108B2Optimizing power usage by factoring processor architectural events to PMU

Publication Date: 2021.10.12 TAHOE RES LTD

AI summary

A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.