Pd Catalyst Electroless Plating for Semiconductor Via Adhesion
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Solution Overview
Problem
Conventional methods for forming metal films on semiconductor substrates, such as vapor deposition or sputtering, result in poor conduction and high yield loss due to thin films on via hole sidewalls and abnormal growth of Au-plated films during electrolytic plating, leading to inadequate adhesion and coating characteristics.
Innovation Solution
A method involving immersion of semiconductor substrates in a Pd activating solution to adhere a Pd catalyst, followed by immersion in a Pd electroless plating solution to form a stable Pd film, which reacts with the substrate to enhance adhesion and film formation on smooth surfaces, including via hole sidewalls, using a Pd electroless plating process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If vapor deposition or sputtering is used to form metal films, then the manufacturing process is simple, but the film thickness on via hole sidewalls becomes too thin causing poor conduction
Solution Approach 1:
The patent introduces a Pd catalyst layer as an intermediary between the semiconductor substrate and the electroless plating solution. This catalyst layer enables the electroless plating reaction to occur uniformly on via hole sidewalls, solving the conduction problem while maintaining process simplicity
Solution Approach 2:
The patent changes the deposition mechanism from physical vapor deposition to chemical electroless plating. This parameter change allows uniform film formation on complex geometries including via hole sidewalls, improving conduction reliability without significantly complicating the manufacturing process
2Ease of manufacture
If vapor deposition or sputtering is used to form metal films, then the process is straightforward, but the film adhesion on semiconductor substrate is insufficient
Solution Approach 1:
The Pd catalyst layer serves as an intermediary that chemically bonds to both the semiconductor substrate and the electroless plated Pd film, creating strong adhesion interfaces while keeping the process straightforward
Solution Approach 2:
The patent creates a composite structure consisting of the semiconductor substrate, Pd catalyst layer, and electroless plated Pd film. This composite approach ensures strong adhesion through chemical bonding while maintaining manufacturing simplicity
3Ease of manufacture
If Au electrolytic plating is performed using vapor deposition or sputtering metal films as power supply layers, then the process can proceed, but the Au-plated film does not grow or grows abnormally in via holes
Solution Approach 1:
The electroless plated Pd film acts as an intermediary power supply layer that enables uniform Au electrolytic plating growth in via holes. This intermediate layer solves the abnormal growth problem while maintaining process feasibility
Solution Approach 2:
The patent performs preliminary electroless plating of Pd on via hole sidewalls before Au electrolytic plating. This preliminary action ensures that the subsequent Au plating grows uniformly, preventing abnormal growth while keeping the overall process feasible
4Device complexity
If conventional vapor deposition or sputtering is used, then the equipment is simple, but the coating characteristics on via hole sidewalls are poor
Solution Approach 1:
The Pd catalyst layer and electroless plating solution work together as intermediaries to achieve uniform coating on via hole sidewalls using simple equipment, eliminating the need for complex deposition systems while improving coating precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of metal films with high coating characteristics and adhesion on semiconductor substrates at low costs, improving conduction and yield by ensuring uniform film deposition and preventing abnormal growth of Au-plated films in via holes.
Implementation Method 1
immersing a semiconductor substrates in a Pd activating solution containing Pd ions so as to adhere a Pd catalyst on a surface of the semiconductor substrate
Implementation Method 2
immersing the semiconductor substrate, on which the Pd catalyst is adhered, in a Pd electroless plating solution so as to form an electroless-plated Pd film on the semiconductor substrate
Implementation Method 3
immersing the semiconductor substrate, on which the Pd catalyst is adhered, in a Pd electroless plating solution
Data Source
AI summary
A method for manufacturing a semiconductor device comprises: immersing a semiconductor substrates in a Pd activating solution containing Pd ions and adhering a Pd catalyst to a surface of the semiconductor substrate; and immersing the semiconductor substrate, to which the Pd catalyst is adhered, in a Pd electroless plating solution and forming an electroless-plated Pd film on the semiconductor substrate.