PDAF Image Sensor ADCs With Reduced SAR Bit Trials
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Solution Overview
Problem
Current analog-to-digital converters (ADCs) in phase-detection autofocus image sensors face challenges in increasing conversion speed while maintaining low power consumption and reducing design complexity and noise.
Innovation Solution
The implementation of adaptive successive approximation register (SAR) techniques in combination with correlated multiple sampling (CMS) in the ADCs of phase-detection autofocus image sensors, which reduces the number of bit trials required for conversion and allows for an increased number of samples in a row-conversion time period, thereby enhancing speed and noise reduction without a proportional increase in ADC sample rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional SAR conversion is used, then conversion accuracy is maintained, but conversion speed is limited due to the number of bit trials required
Solution Approach 1:
The patent segments the ADC conversion process into two distinct phases: a first row conversion that processes all pixels with full N-bit precision, and subsequent row conversions that process only M least significant bits (LSBs) and combine them with pre-determined most significant bits (MSBs). This segmentation allows most rows to use the faster reduced conversion while maintaining overall accuracy through the initial full conversion, thereby increasing conversion speed without sacrificing precision.
Solution Approach 2:
The patent performs preliminary action by completing a full N-bit conversion for the first row of pixels before processing subsequent rows. The MSBs obtained from this preliminary conversion are then reused for all subsequent rows, eliminating the need to re-determine these bits. This preliminary action significantly reduces the conversion time for subsequent rows while maintaining accuracy, directly addressing the speed-time contradiction.
2Measurement precision
If the number of samples per row-conversion time period is increased, then noise reduction is improved, but power consumption increases
Solution Approach 1:
The patent changes the conversion parameters dynamically: for the first row, it uses full N-bit conversion, and for subsequent rows, it uses reduced M-bit conversion for only the LSBs. This parameter change allows the system to process more samples within the same row-conversion time period by reducing the conversion complexity for most rows, thereby improving noise reduction through increased sampling without proportionally increasing power consumption.
3Speed
If ADC sample rate is increased to improve conversion speed, then conversion speed improves, but design complexity and power consumption increase
Solution Approach 1:
The patent introduces dynamic behavior to the ADC conversion process by switching between two conversion modes: full N-bit conversion for the first row and reduced M-bit conversion for subsequent rows. This dynamic approach allows the system to achieve higher effective conversion speeds without requiring a proportionally higher ADC sample rate, as the reduced conversion mode processes most rows much faster. The system adapts its conversion depth based on whether it is processing the first row or subsequent rows, optimizing performance without increasing hardware complexity.
Data Source
AI summary
Embodiments of the present disclosure provide ADCs particularly suitable for PDAF image sensors, which ADCs may have an increased speed and/or reduced design complexity and power consumption compared to conventional implementations. An example ADC for a PDAF image sensor is configured to implement modified SAR techniques which reduce the number of bit trials required for conversion, and enable increased number of samples in a row-conversion time period of the image sensor. The ADC may implement the modified SAR techniques in combination with CMS in pixel readout signal chain, which may reduce noise without a proportionate increase in ADC sample rate.