PDCCH Block Interleaving With Fewer Null Entries

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Solution Overview

Problem

Current block interleaving solutions for NR PDCCHs are inefficient due to the need for dummy entries and complex CCE-to-REG mapping, which increases computational complexity and does not directly generate interleaving sequences effectively.

Innovation Solution

A network node generates an interleaver sequence for a control resource set with an input sequence and null entries, determining the number of rows for the interleaving matrix such that the number of null entries is minimized and no more than the number of columns, allowing for efficient interleaving by writing and reading the sequence in a rectangular matrix while skipping null entries.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dummy entries are added to the interleaving matrix to handle non-divisible REG bundle counts, then the interleaving can be completed, but the computational complexity increases and processing efficiency decreases

Engineering Contradiction:
Improveinterleaving completionVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the problematic dummy entries from the interleaving process. Instead of adding null entries to force matrix completion, the invention modifies the interleaving algorithm to naturally handle cases where the number of REG bundles is not divisible by the number of rows, eliminating the need for dummy entries and their associated computational overhead.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameters of the interleaving process by allowing the number of rows in the interleaving matrix to be dynamically selected from allowed values to achieve proper divisibility. This parameter adjustment enables the system to adapt the matrix dimensions to match the input size, avoiding the need for dummy entries while maintaining reliable interleaving completion.

Inventive Principle:
Principle #35Parameter changes

2Ease of manufacture

If a fixed interleaving matrix structure is used, then the implementation is simple, but it cannot handle variable numbers of REG bundles efficiently

Engineering Contradiction:
Improveimplementation simplicityVSAvoidhandling variable REG bundles
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent introduces dynamics to the interleaving matrix structure by allowing the number of rows to be selected from allowed values based on the input size. This dynamic adjustment enables the fixed matrix structure to adapt to variable numbers of REG bundles, maintaining both implementation simplicity and versatility.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent creates a universal interleaving solution that can handle any number of REG bundles by selecting appropriate matrix dimensions from allowed values. This multi-functional approach allows the same interleaving algorithm to work efficiently across different configurations without requiring separate handling for each case.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Productivity

If the number of rows in the interleaving matrix is increased, then more REG bundles can be processed, but the number of null entries increases

Engineering Contradiction:
Improveprocessing capacityVSAvoidnull entries
Core Design Contradiction:
ProductivityVSLoss of substance

Solution Approach 1:

The patent changes the parameter selection strategy by choosing the number of rows from allowed values that optimize the balance between processing capacity and null entry minimization. This parameter optimization ensures that the interleaving matrix is configured to handle the maximum number of REG bundles while keeping null entries to a minimum.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies local quality optimization by selecting different numbers of rows from allowed values based on the specific input size. This localized optimization ensures that each interleaving operation uses the most appropriate matrix configuration, minimizing null entries for each specific case while maintaining high processing capacity.

Inventive Principle:
Principle #3Local quality

Data Source

PatentEP3738238B1Wireless communication block interleaving
Publication Date: 2022.09.21 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • EP3738238B1 patent drawingFigure 1
  • EP3738238B1 patent drawingFigure 2
  • EP3738238B1 patent drawingFigure 3

AI summary

Apparatuses and methods are disclosed for block interleaving. In one embodiment, a method includes generating an interleaver sequence for a control resource set, CORESET, configuration for a physical downlink control channel, the interleaver sequence associated with an interleaving matrix; optionally, for each one of an allowed value of number of rows for the interleaving matrix, determining a number of null entries to be added to the interleaving matrix; and selecting a number of rows, R, for the interleaving matrix such that the number of null entries to be added to the interleaving matrix is: no more than a number of columns, C, of the interleaving matrix; and optionally, the smallest among the numbers of null entries determined for each of the allowed values of number of rows for the interleaving matrix. In another embodiment, a method includes decomposing the interleaver sequence.