Page Directory Entry Cache for TLB Lookup Optimization
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Solution Overview
Problem
In virtual memory systems, determining the correct page size for address translation is inefficient due to the need to check multiple possible page sizes in the translation lookaside buffer (TLB), leading to increased resource costs and potential performance slowdowns.
Innovation Solution
The method involves performing a Page Directory Entry Cache (PDEC) lookup to identify possible page sizes and update them, followed by a TLB lookup with a reduced set of likely page sizes, thereby reducing the number of TLB checks required and determining if a page walk is necessary.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a system attempts to look up a translation in a TLB by trying every possible page size, then the translation can be found, but the time and resource costs increase significantly
Solution Approach 1:
The patent performs a preliminary PDEC lookup before the TLB lookup to determine the correct page size in advance. This preliminary action provides the offset bit information needed to configure the TLB lookup correctly, avoiding the need to try every possible page size and thereby reducing the time and resource costs while maintaining translation lookup accuracy.
2Adaptability or versatility
If multiple page sizes are supported in the system, then the system is more versatile, but the complexity of address translation increases
Solution Approach 1:
The patent introduces the PDEC as an intermediary structure between the virtual address and the TLB lookup. The PDEC stores offset information that acts as a mediator to guide the TLB lookup process, enabling the system to support multiple page sizes while simplifying the translation complexity by providing clear guidance on which page size to use for each virtual address.
3Reliability
If the system performs complete TLB lookups for all possible page sizes, then no translation errors occur, but the resource costs increase
Solution Approach 1:
The patent performs a preliminary PDEC lookup to determine the correct page size before executing the TLB lookup. This preliminary action ensures that the subsequent TLB lookup is performed with the correct configuration, eliminating the need to perform multiple redundant lookups and thereby reducing energy consumption while maintaining translation accuracy.
4Measurement precision
If the offset size is not determined correctly, then the page size assumption is wrong, but identifying the correct offset requires knowing the page size in advance
Solution Approach 1:
The patent uses the PDEC as an intermediary that breaks the circular dependency between page size determination and offset identification. The PDEC stores offset information that can be retrieved independently of the page size assumption, providing the necessary information to correctly identify the offset and determine the actual page size without requiring knowledge in advance.
Data Source
AI summary
A page directory entry cache (PDEC) can be checked to potentially rule out one or more possible page sizes for a translation lookaside buffer (TLB) lookup. Information gained from the PDEC lookup can reduce the number of TLB checks required to conclusively determine if the TLB lookup is a hit or a miss.