PDM Bitstream Conversion With Delayed Return-to-Zero Timing
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Solution Overview
Problem
Digital-to-analog converters (DACs) face challenges in achieving high signal-to-noise ratio (SNR) due to Intersymbol Interference (ISI), particularly in oversampled DACs, where the return-to-zero (RTZ) approach introduces full-scale steps and sensitivity to clock jitter, degrading performance.
Innovation Solution
A bitstream converter processes 1-bit pulse density modulated (PDM) bitstream signals using a return-to-zero clock with a frequency higher than the sampling frequency, outputting a 1-bit return-to-zero signal that is free of ISI, and employs a finite impulse response filter to minimize signal power loss and remove high-frequency noise, thereby increasing SNR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If return-to-zero (RTZ) approach is used in oversampled DACs, then ISI is eliminated, but full-scale steps are introduced and sensitivity to clock jitter increases, degrading performance
Solution Approach 1:
The patent changes the timing parameters of the bit waveform by introducing a delayed return-to-zero scheme where the waveform returns to zero at a delayed time point rather than immediately. This parameter adjustment reduces the magnitude of full-scale steps while maintaining ISI elimination, and the reduced step size decreases sensitivity to clock jitter, thereby resolving the contradiction between reliability and manufacturing precision
Solution Approach 2:
The patent introduces dynamic adjustment of the return-to-zero timing based on the input signal characteristics. By making the return-to-zero time dynamic rather than fixed, the system can adapt to different signal conditions, reducing full-scale steps when possible while maintaining the ISI-free property, thus improving output accuracy without sacrificing reliability
2Reliability
If RTZ code is used to reduce ISI, then area under waveform becomes independent of previous bit values, but large step sizes increase sensitivity to clock edge timing errors
Solution Approach 1:
The patent modifies the timing parameter of the return-to-zero transition by introducing a delay. This changes the waveform shape such that while still returning to zero (maintaining independence), the transition is spread over a longer time period, reducing the instantaneous step size and thereby decreasing sensitivity to clock edge timing errors
Solution Approach 2:
The delayed return-to-zero approach acts as a cushioning mechanism by preparing the waveform to return to zero more gradually rather than abruptly. This beforehand preparation reduces the impact of timing errors by cushioning the transition, thus protecting against clock jitter while maintaining waveform independence
Data Source
AI summary
A bitstream converter for converting a 1-bit pulse density modulated (PDM) bitstream signal into an analog audio signal, the bitstream converter comprising: a processor configured to process the 1-bit PDM bitstream signal using a return to zero clock having a frequency higher than a sampling frequency of the 1-bit PDM bitstream signal to output a corresponding 1-bit return to zero signal, wherein the processor is configured to process the 1-bit PDM signal to ensure a portion of each bit of the 1-bit PDM bitstream signal is zero for a duration which is based on the frequency of the return to zero clock; and signal processing means configured to extract the analog audio signal from the 1-bit return to zero signal by filtering the 1-bit return to zero signal.