Dual PDM Microphone Clock Interface for Lower Power Operation

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Solution Overview

Problem

Conventional dual PDM microphone systems waste power as both microphones are clocked even when only one is in use, leading to increased power consumption and system complexity.

Innovation Solution

A three-signal interface is introduced, where each PDM microphone receives a separate PDMCLK signal while sharing a single common PDMDAT line, allowing each microphone to operate independently when the other is powered down.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a shared clock signal is used for both microphones in a dual PDM microphone system, then system complexity is reduced, but power consumption increases because both microphones are clocked even when only one is in use

Engineering Contradiction:
Improvesystem complexityVSAvoidpower consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent segments the clock signal distribution by providing separate PDMCLK inputs to each microphone channel. This allows independent clocking of each microphone, enabling the system to clock only the active microphone(s) and reduce power consumption while maintaining full functionality. The segmentation of the clock distribution architecture resolves the contradiction between system complexity and power consumption.

Inventive Principle:
Principle #1Segmentation

2Object-affected harmful factors

If digital MEMS microphones are used instead of analog microphones, then noise immunity is improved, but power consumption increases due to digital switching

Engineering Contradiction:
Improvenoise immunityVSAvoidpower consumption
Core Design Contradiction:
Object-affected harmful factorsVSUse of energy by moving object

Solution Approach 1:

The patent implements periodic action by enabling or disabling the clock signal to microphones based on operational needs. By clocking microphones only when required rather than continuously, the system maintains the noise immunity benefits of digital MEMS microphones while significantly reducing power consumption through periodic activation rather than continuous operation.

Inventive Principle:
Principle #19Periodic action

3Reliability

If both microphones in a dual PDM system are clocked simultaneously, then full system functionality is maintained, but unnecessary power usage increases

Engineering Contradiction:
Improvesystem functionalityVSAvoidunnecessary power usage
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies dynamics by making the clock signal distribution adaptive and configurable. The system can dynamically adjust which microphones are clocked based on operational requirements, allowing full functionality when both microphones are needed while reducing power consumption when only one is active. This dynamic control resolves the contradiction between maintaining reliability and reducing energy loss.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250168562A1Digital PDM Microphone Interface
Publication Date: 2025.05.22 SYNTIANT
  • US20250168562A1 patent drawing
  • US20250168562A1 patent drawing
  • US20250168562A1 patent drawing

AI summary

A clocking technique for reducing the power of PDM microphones in dual microphone systems is disclosed. A clock for a conventional PDM microphone (PDMCLK) is provided by another source. PDM microphones send serial data (PDMDAT) on the rising (“Right”) or falling (“Left”) edge of the PDMCLK clock, depending on how the microphone is configured. In a dual PDM microphone configuration, the microphones alternate sending data on the rising edges (transitions to logic-1) and falling edges (transitions to logic-0) of PDMCLK. Typically, Complementary Metal-Oxide-Semiconductor (CMOS) logic is used to transmit or drive the clock signal to the microphones. CMOS drivers consume power primarily when they transition from a logic-0 to a logic-1 or from a logic-1 to a logic-0. Thus, a free-running clock signal will produce the highest CMOS power consumption. In a dual PDM microphone system, it is desirable to operate in a low power mode with a single microphone at times and to operate with the full functionality (and power consumption) of both microphones at other times. In a conventional system, both PDM microphones share both the PDMDAT and PDMCLK signal lines. Thus both microphones must be clocked even if only one is being used. This wastes power in both the PDMCLK output buffer (driving both loads even if one is not being used) as well as in the unused microphone (where all of the clock circuits are active and switching). A novel PDM microphone interface is disclosed that provides a three signal interface comprising a separate PDMCLK signal to each microphone while maintaining a single common PDMDAT line.