Power Distribution Network Layer for Active-on-Active Die Stack IR Drop Reduction
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Solution Overview
Problem
In active-on-active die stacks, voltage drop along power rails leads to significant current-resistance (IR) loss, making it challenging to maintain performance and reduce power consumption, especially in sub-20 nanometer semiconductor process nodes.
Innovation Solution
A power distribution network (PDN) metalization layer is introduced between upper and lower metal layers, with an 'early off-ramp' buss and thicker intermediate metalization levels to reduce IR drop, and a chimney interim buss path is used to bypass chimney metalization levels, providing a lower resistance path for power and ground distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional power distribution networks are used in active-on-active die stacks, then device density is increased through stacking, but voltage drop and IR loss increase significantly
Solution Approach 1:
The patent introduces an intermediate power distribution network layer in the vertical dimension between upper and lower metal layers. This third-dimensional approach to power distribution reduces current path length and resistance by providing localized power delivery at multiple vertical levels, rather than relying solely on planar distribution layers.
Solution Approach 2:
The intermediate metalization layer acts as an intermediary power distribution network between the upper and lower power distribution layers. This intermediate layer provides additional current pathways and reduces the overall resistance by distributing power more evenly across the vertical stack, thereby reducing IR losses.
2Loss of energy
If thicker intermediate metalization levels are added to reduce IR drop, then power distribution efficiency improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent applies thicker metalization specifically in the intermediate power distribution layer where it is most needed for reducing IR drop, rather than uniformly thickening all metal layers. This localized approach to metalization optimization reduces overall complexity while achieving the desired power distribution improvement.
Solution Approach 2:
The patent modifies the thickness parameter of the intermediate metalization layer to optimize power distribution. By changing this specific geometric parameter, the design achieves reduced IR drop without requiring a complete redesign of the entire metalization stack, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces IR drop by at least 20% without increasing the area or cost, effectively addressing the voltage drop issue and improving power distribution efficiency in die stacks.
Implementation Method 1
a through-substrate via extending between a top surface and a bottom surface of the first substrate
Implementation Method 2
A power distribution network layer of the second stack structure is located between lower layers and upper layers of the plurality of metal layers thereof
Implementation Method 3
The first die and the second die each have a plurality of metal layers formed in a plurality of inter-level dielectric layers to provide a first stack structure and a second stack structure, respectively, for electrical conductivity
Data Source
AI summary
Active-on-active microelectronic devices are described. For example, a first die is on a second die with a bottom surface of a first substrate facing a top surface of a second substrate, respectively, to provide a die stack. The first and second dies each have metal layers in ILD layers to provide a first stack structure and a second stack structure, respectively. The first stack structure is interconnected to an upper end of a TSV of the first die. A metal layer of the second stack structure near a bottom surface of the first substrate is interconnected to a lower end of the TSV. A power distribution network layer of the second stack structure is located between lower and upper layers of the metal layers thereof. A transistor located at least in part in the second substrate is interconnected to the power distribution network layer to receive supply voltage or ground.