Interleaved PDN Via Layout for Lower Loop Inductance
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Solution Overview
Problem
Existing power delivery network (PDN) designs face challenges in reducing loop inductance without increasing core thickness, leading to noise interference and instability in voltage delivery.
Innovation Solution
Arranging power vias in close proximity to ground vias to reduce loop inductance by maintaining a short return current path, thereby minimizing loop area and loop inductance without increasing core thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If core thickness is increased to reduce loop inductance, then loop inductance is reduced, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent transitions from modifying the vertical dimension (core thickness) to modifying the horizontal dimension (via arrangement pattern). By arranging power vias and ground vias in an interleaved alternating pattern in the planar direction, the invention reduces loop area and loop inductance without increasing core thickness, thus resolving the contradiction between reducing inductance and avoiding increased device complexity.
2Object-affected harmful factors
If via arrangement is optimized to reduce loop area, then noise interference is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the via arrangement into alternating power vias and ground vias in an interleaved pattern. This segmentation creates multiple small loop areas instead of one large loop, reducing noise interference through minimized loop area while maintaining a regular, repeating pattern that is easier to manufacture with standard precision compared to custom optimized arrangements.
3Reliability
If power delivery efficiency is enhanced through better via arrangement, then voltage stability improves, but device complexity increases
Solution Approach 1:
The patent merges the functions of power delivery and ground return into a unified interleaved via pattern where power vias and ground vias alternate. This merging creates a compact structure that simultaneously provides low loop inductance, good voltage stability, and simplified design compared to separate power and ground via arrangements, thus improving voltage stability without proportionally increasing device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This arrangement maintains stable voltage levels, reduces noise interference, and enhances power delivery efficiency in high-speed and high-frequency electronic systems.
Implementation Method 1
Arranging power vias in close proximity to ground vias to reduce loop inductance by maintaining a short return current path, thereby minimizing loop area and loop inductance
Data Source
AI summary
A power delivery network includes an array of first vias arranged on a particular plane of the power delivery network to form a particular shape on the particular plane. The power delivery network further includes an array of second vias with at least one via of the array of second vias arranged at a location within the particular shape on the particular plane.