PDN Voltage Stability via Clock Frequency Ramping
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Solution Overview
Problem
Dynamic frequency scaling in power distribution networks (PDNs) leads to voltage overshoot and droop issues during clock switching, causing malfunctions in coupled circuits due to rapid changes in clock frequencies.
Innovation Solution
Implementing a frequency ramp circuit that gradually ramps down the frequency of the clock signal before disabling the current input clock signal and ramps up the frequency when enabling the new input clock signal, using techniques such as frequency division or pulse swallowing to reduce the rate of change in current load on the PDN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If dynamic frequency scaling is implemented to change clock frequency based on use cases, then power consumption is optimized, but voltage overshoot and droop occur during clock switching causing circuit malfunctions
Solution Approach 1:
The patent applies preliminary action by ramping down the frequency of the outgoing clock signal before disabling it, and ramping up the frequency of the incoming clock signal after enabling it. This preparatory frequency adjustment prevents sudden load changes that cause voltage overshoot and droop, thereby maintaining circuit stability during dynamic frequency scaling operations.
Solution Approach 2:
The patent implements dynamics by transitioning from abrupt clock frequency switching to gradual frequency ramping. The frequency ramping process dynamically adjusts the clock frequency over time using frequency division or pulse swallowing techniques, smoothing the transition and preventing harmful voltage transients while maintaining the ability to respond to changing power requirements.
2Speed
If clock frequency is switched abruptly between different frequencies, then response time is fast, but voltage overshoot and droop occur causing PDN instability
Solution Approach 1:
The patent applies preliminary action by preparing the clock frequency transitions in advance through ramping operations. Before disabling a clock signal, its frequency is gradually reduced; after enabling a new clock signal, its frequency is gradually increased. This preliminary frequency adjustment prevents sudden PDN load changes while maintaining relatively fast overall switching response.
Solution Approach 2:
The patent uses frequency ramping as an intermediary process between the initial clock switching command and the final steady-state frequency. This intermediate frequency adjustment phase acts as a buffer that smooths the transition, preventing direct abrupt changes that would cause voltage overshoot and droop in the PDN.
3Reliability
If frequency ramping is implemented to smooth clock transitions, then voltage overshoot and droop are reduced, but clock switching time increases
Solution Approach 1:
The patent applies partial action by implementing frequency ramping only during necessary clock transitions and using configurable ramp rates. The ramping process can be adjusted to balance between smoothing voltage transitions and minimizing switching time, applying the degree of frequency adjustment needed without unnecessary delay.
Solution Approach 2:
The patent uses parameter changes by allowing the frequency ramping rate to be configured and adjusted. By changing the ramp rate parameter, the system can optimize the balance between voltage stability (smoother transitions require slower ramping) and switching time (faster ramping reduces delay), adapting to different operational requirements.
Data Source
Figure 1A~1B
Figure 1C
Figure 2
AI summary
Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In certain embodiments, overshoot is mitigated by ramping down a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an active mode to an idle mode. In certain embodiments, droop is mitigated by ramping up a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an idle mode to an active mode.