Pseudo-Dual Port Memory Write Driver Circuitry

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Solution Overview

Problem

Dual port memories consume significant area, prohibiting their use in wireless communications devices, and pseudo-dual port memories have increased cycle times, inhibiting high-performance applications.

Innovation Solution

A method and circuitry for a pseudo-dual port memory that pre-charges bitline pairs coupled to unselected columns during a write operation after a read operation, concurrently pulling down bitline pairs coupled to a selected column, using a merged pre-charge/write switcher/driver circuit to reduce cycle time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If pseudo-dual port memory is used instead of dual port memory, then memory area is reduced, but cycle time increases

Engineering Contradiction:

Improvememory footprintVSAvoidcycle time

Core Design Contradiction:

Area of stationary objectVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-charging bitline pairs coupled to unselected columns during the pre-charge operation phase, before the write operation begins. This advance preparation of bitlines for future write operations allows the memory to reduce cycle time while maintaining the area benefits of pseudo-dual port architecture.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements continuity of useful action by overlapping the pre-charge operation with the write driver operation. The merged pre-charge/write switcher/driver circuit enables these operations to occur concurrently rather than sequentially, eliminating idle time and improving overall memory performance while maintaining reduced area footprint.

Inventive Principle:

Principle #20Continuity of useful action

2Adaptability or versatility

If sequential read then write operation is performed in PDP memory, then dual port functionality is emulated, but cycle time increases

Engineering Contradiction:

Improvedual port functionalityVSAvoidcycle time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent merges the pre-charge operation and write driver operation into a single merged pre-charge/write switcher/driver circuit. This combining of functions allows both operations to occur simultaneously during the same time period, enabling the memory to emulate dual port functionality while reducing the cycle time penalty associated with sequential operations.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces dynamic operation by allowing the memory to flexibly switch between different operational modes. The merged circuit can dynamically handle both pre-charge and write operations based on the current state and requirements, enabling adaptive timing that reduces cycle time while maintaining versatility.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10916275B1Write driver and pre-charge circuitry for high performance pseudo-dual port (PDP) memories

Publication Date: 2021.02.09 QUALCOMM INC

AI summary

A method for operating a pseudo-dual port (PDP) memory is described. The method includes pre-charging bitline pairs BL and BLB coupled to unselected columns of the PDP memory according to a write operation during a pre-charge operation after a read operation of the PDP memory. The method also includes concurrently pulling-down a bitline pair BL and BLB coupled to a selected column of PDP memory according to the write operation.