PDP SRAM Burst-Mode Address Comparator for Low-Power Reads

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Solution Overview

Problem

Existing address comparators for SRAMs are not compatible with the double-pumped timing of pseudo-dual-port (PDP) operation, limiting the implementation of burst-mode operations in PDP SRAMs, which aims to provide flexibility like dual-port SRAMs while maintaining the density of traditional six-transistor bitcell architectures.

Innovation Solution

A burst-mode address comparator is developed that includes a plurality of single-bit comparators with multiplexers for selecting read and write address bits and logic gates for comparison, along with a combining circuit to control memory operations, enabling burst-mode read operations without reasserting the word line and discharging bit lines, thus reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional address comparator is used in PDP SRAM, then the device complexity is reduced, but the adaptability to burst-mode operation is lost

Engineering Contradiction:

Improveburst-mode operation capabilityVSAvoidaddress comparator complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The address comparator is divided into multiple single-bit comparators, each handling one bit of the address comparison. This segmentation allows the comparator to be reset between random and burst modes, enabling adaptability to different operation modes while keeping each individual comparator simple.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The address comparator is made dynamic by introducing a reset mechanism that changes its state based on the operation mode. The comparator can be reset after a random read operation, allowing it to function in burst-mode where address comparison is needed only initially, thus adapting to different operational requirements.

Inventive Principle:

Principle #15Dynamics

2Ease of operation

If random read operation is performed repeatedly, then the memory can access any bitcell, but power consumption increases due to repeated word line assertion and bit line discharge

Engineering Contradiction:

Improvememory access flexibilityVSAvoidpower consumption

Core Design Contradiction:

Ease of operationVSUse of energy by moving object

Solution Approach 1:

A random read operation is performed preliminarily to latch the data in sense amplifiers. Subsequent burst reads can then access the same row without re-asserting the word line or discharging bit lines, as the data is already latched, thus reducing power consumption while maintaining access flexibility.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The burst-mode read operation continues the useful action of reading data from the same row without interrupting the latched state in sense amplifiers. This continuous action avoids the energy-consuming steps of word line assertion and bit line discharge, maintaining operational flexibility while conserving power.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS11640838B2Pseudo-dual-port SRAM with burst-mode address comparator

Publication Date: 2023.05.02 QUALCOMM INC

AI summary

A memory is provided that is configured to practice two different modes of read operation, such as both a normal read operation and a burst-mode read operation. In one example, the memory is a pseudo-dual-port memory. The memory may include an address comparator to perform a time-division multiplexing to first compare a read address to a stored address and then to compare a write address to the stored address.