PDP SRAM Pre-Charge Circuit for NBTI-Stable Cycle Time

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Solution Overview

Problem

The negative bias temperature instability (NBTI) effect causes prolonged bit line recovery times in two-port static random access memory (PDP SRAM) circuits, leading to cycle time degradation due to increased threshold voltage shifts in PMOS transistors, which affects the reliability and functionality of the memory device.

Innovation Solution

Implementing multiple pre-charge circuits, including a first and second pre-charge circuit, where the first pre-charge circuit is activated during standby mode to pre-charge bit lines while the second pre-charge circuit maintains a high state to minimize NBTI impact, and an equalizer circuit to equalize bit line voltages, thereby reducing recovery time and mitigating cycle time degradation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If a single pre-charge circuit is used to pre-charge bit lines, then the bit line recovery time is reduced, but the NBTI effect causes threshold voltage shifts in PMOS transistors leading to cycle time degradation

Engineering Contradiction:

Improvebit line recovery timeVSAvoidcycle time stability

Core Design Contradiction:

Loss of timeVSReliability

Solution Approach 1:

The patent divides the single pre-charge circuit into multiple pre-charge circuits (first pre-charge circuit and second pre-charge circuit). The first pre-charge circuit uses PMOS transistors for pre-charging bit lines, while the second pre-charge circuit uses NMOS transistors to compensate for NBTI effects. This segmentation allows each circuit to have specialized functions that collectively solve the contradiction between recovery time and cycle time stability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the transistor type parameter from uniform PMOS to a combination of PMOS and NMOS transistors in different pre-charge circuits. By using NMOS transistors in the second pre-charge circuit, the system compensates for the threshold voltage shifts caused by NBTI in PMOS transistors, thereby maintaining cycle time stability while still achieving fast bit line recovery.

Inventive Principle:

Principle #35Parameter changes

2Speed

If PMOS transistors are used in pre-charge circuits for fast switching, then switching speed is improved, but NBTI effect causes threshold voltage shifts leading to increased recovery time

Engineering Contradiction:

Improveswitching speedVSAvoidbit line recovery time

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The patent converts the harmful NBTI effect into a beneficial compensation mechanism. By intentionally introducing a second pre-charge circuit with NMOS transistors that experience opposite bias conditions, the system uses the complementary threshold voltage shifts to cancel out the NBTI-induced delays in the first pre-charge circuit, thereby maintaining fast switching speeds while compensating for recovery time increases.

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

3Reliability

If multiple pre-charge circuits are implemented to mitigate NBTI effect, then cycle time stability is improved, but device complexity increases

Engineering Contradiction:

Improvecycle time stabilityVSAvoidpre-charge circuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the functions of multiple pre-charge circuits into a unified system where the first pre-charge circuit (PMOS-based) and second pre-charge circuit (NMOS-based) work together. By combining these circuits with complementary transistor types, the system achieves cycle time stability through NBTI compensation while sharing common control logic and bit line connections, thereby reducing the overall complexity increase that would result from completely separate circuits.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20260031141A1Systems and methods to mitigate cycle time degradation by NBTI effect on PDP SRAM

Publication Date: 2026.01.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A memory circuit includes a memory array comprising a plurality of memory cells. The memory circuit includes a first pre-charge circuit coupled to at least one access line electrically connected to the plurality of memory cells and configured to be in a first state during a standby mode of the memory array. The memory circuit includes a second pre-charge circuit coupled to the at least one access line and configured to be in a second state during the standby mode.