Interconnection Protocol PDU Spacing for Multi-Lane Complexity Reduction
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Solution Overview
Problem
The complexity of hardware circuit design and maintenance increases with the need for multiple lanes in interconnection protocols like UniPro, particularly in high-speed data transmission scenarios, such as those in mobile devices, due to the complexity of error handling and lane management.
Innovation Solution
The method involves allocating start-of-frame (SOF)-included protocol data units (PDUs) to a designated lane with a PDU distance greater than or equal to the product of the maximum bus width and the number of active lanes, reducing the complexity of the hardware protocol engine and decoder in the data link layer receiver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple lanes are supported in the interconnection protocol, then the data transmission capacity and speed are improved, but the complexity of the processing circuit becomes high
Solution Approach 1:
The patent segments the data transmission process by introducing a specific ordering rule where SOF-included PDUs are allocated to designated lanes with controlled spacing. This segmentation approach divides the complex multi-lane handling into manageable units, allowing the receiver to process lanes independently rather than managing all lanes simultaneously, thus reducing circuit complexity while maintaining multi-lane transmission capacity
Solution Approach 2:
The patent applies preliminary action by establishing the PDU distance constraint before transmission occurs. The sender pre-configures the spacing between SOF-included PDUs to be at least equal to the product of maximum bus width and number of active lanes. This preliminary arrangement ensures that error control operations can be performed sequentially and independently at the receiver, avoiding the need for complex simultaneous error handling across multiple lanes
2Speed
If a wider bus width is implemented, then the data transmission speed is improved, but the complexity of the processing circuit becomes high
Solution Approach 1:
The patent changes the parameter of PDU spacing based on the bus width and number of lanes. By setting the minimum PDU distance to equal the product of maximum bus width and number of active lanes, the system adapts the transmission parameters to match the hardware configuration. This allows wider bus widths to be utilized for higher speed transmission while the corresponding increased PDU spacing automatically simplifies the error control logic by reducing interference between parallel data paths
3Productivity
If four lanes are configured, then the data transmission capacity is improved, but the error control complexity increases
Solution Approach 1:
The patent segments the error control task by ensuring that SOF-included PDUs are spaced sufficiently apart in the transmission sequence. This segmentation allows the receiver's error control circuit to process each PDU independently without needing to handle complex inter-lane error interactions, thereby maintaining manageable error control complexity even with four active lanes providing high transmission capacity
Solution Approach 2:
The patent introduces the PDU distance constraint as an intermediary mechanism between the multi-lane transmission system and the error control function. This intermediary spacing rule acts as a buffer that decouples the error control complexity from the number of lanes, allowing four lanes to operate in parallel for high capacity while the error control logic processes each PDU sequentially with simplified logic
Data Source
AI summary
A method for data processing of an interconnection protocol, a controller and a storage device, the method comprising in processing of frame sending by a first device to a second device: allocating a plurality of start-of-frame (SOF)-included protocol data units (PDUs) to a designated lane among a plurality of active lanes of the first device; and configuring a PDU distance among the plurality of start-of-frame (SOF)-included protocol data units to be greater than or equal to a product of a maximum bus width of a lane of the interconnection protocol and a quantity of the plurality of active lanes. Accordingly, the method can help greatly reduce the complexity of the hardware protocol engine implemented under the interconnection protocol, especially the complexity of the decoder in the data link layer receiver, thus reducing the difficulty of research and development, verification and maintenance.