Packet Delay Variation Mitigation in Network Devices

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Solution Overview

Problem

Conventional packet-based synchronization methods are sensitive to packet delay variation (PDV), which degrades clock signal quality, and existing mitigation approaches require protocol awareness or active modification of synchronization packets, or rely on constant packet rates and timestamps.

Innovation Solution

A method and apparatus that timestamp event messages with a local internal clock, calculate time offsets, and adjust transmission delays to minimize PDV by recording maximum observed delays and adjusting internal transmission times at network devices without requiring protocol awareness or active participation in the timing protocol.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional packet-based synchronization methods (NTP or PTP) are used, then clock synchronization is achieved, but packet delay variation degrades the quality of recovered clock signals

Engineering Contradiction:
Improveclock signal qualityVSAvoidsensitivity to packet delay variation
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent applies preliminary action by measuring and recording the maximum observed delay before it affects clock signal recovery. The system proactively captures delay characteristics in advance and uses this information to compensate for PDV effects, rather than reacting after degradation occurs. This is implemented through the maximum observed delay recording mechanism that prepares compensation data beforehand.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If every node in the network actively modifies the synchronization packet stream (e.g., PTP transparent clocks), then packet delay variation is mitigated, but device complexity and protocol awareness requirements increase

Engineering Contradiction:
Improvepacket delay variation mitigationVSAvoidprotocol awareness requirement
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the PDV mitigation function from the protocol layer and implements it as a separate, independent mechanism. Instead of requiring every node to understand and actively participate in the timing protocol, the system extracts delay measurement and compensation functions that operate independently of protocol awareness. This allows passive participation while achieving active mitigation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary mechanism (maximum observed delay recording and compensation) that mediates between the raw packet stream and the clock recovery process. This intermediary layer handles the complexity of PDV mitigation centrally, allowing network devices to forward packets without deep protocol understanding while still achieving mitigation through the intermediary compensation mechanism.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If traffic management techniques are used to minimize delay in each device, then fixed delay is achieved, but adaptability to varying network conditions is reduced

Engineering Contradiction:
Improvefixed delayVSAvoidadaptability to network conditions
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The patent applies dynamics by making the delay compensation adaptive rather than fixed. The system dynamically adjusts compensation based on recorded maximum observed delays, allowing it to adapt to varying network conditions. This dynamic approach replaces static traffic management techniques with a flexible mechanism that responds to actual measured delays.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9596072B2Method and apparatus for mitigation of packet delay variation
Publication Date: 2017.03.14 ADTRAN NETWORKS SE
  • US9596072B2 patent drawing
  • US9596072B2 patent drawing
  • US9596072B2 patent drawing

AI summary

An apparatus for mitigation of packet delay variation, PDV, in a packet-based network, comprising an ingress port to receive event messages, each message being timestamped with a local ingress timestamp at the instant of reception of the message using a local internal clock; an extraction unit to extract a timestamp embedded in the received message; a computation unit to calculate a time offset between the extracted embedded timestamp and the local ingress timestamp of the received event message to record the calculated time offset as a maximum observed delay, if the calculated time offset exceeds a previously recorded maximum observed delay, the computation unit adjusting an internal transmission delay time before onward transmission of the event message from an egress port depending on a time difference between recorded maximum observed delay and calculated time offset of the event message to minimize the packet delay variation, PDV, at the egress port.