Hardware PE State Save-Restore Using Sequencing and Routing

Solution Overview

Problem

Conventional software-based and retention flop-based solutions for saving and restoring processing element (PE) architecture state information result in high latency, increased power consumption, and circuit area due to slow software access and the need for additional hardware resources.

Innovation Solution

A hardware-based approach for saving and restoring PE architecture state information using a sequencing element and routing interface to manage state transitions without lengthy software-based reads and writes, allowing parallel processing and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If software-based solutions are used for saving and restoring PE architecture state information, then the system can maintain state information, but latency increases and power consumption increases

Engineering Contradiction:

Improvestate information preservationVSAvoidlatency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent replaces software-based save/restore mechanisms with a hardware-based system using sequencing elements and routing interfaces. This substitution of mechanical/software systems with hardware circuits eliminates software access latency and enables parallel processing of state information, directly resolving the latency issue while maintaining reliability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces routing interfaces as intermediary components that facilitate efficient data transfer between processing elements and memory. These intermediaries optimize the save/restore process by providing dedicated hardware pathways, reducing the time required for state information transfer compared to general-purpose software access.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If software-based solutions are used for saving and restoring PE architecture state information, then the system can maintain state information, but power consumption increases

Engineering Contradiction:

Improvestate information preservationVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent replaces software-based save/restore mechanisms with a hardware-based system using sequencing elements and routing interfaces. This substitution of mechanical/software systems with hardware circuits eliminates software access latency and enables parallel processing of state information, directly resolving the latency issue while maintaining reliability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces routing interfaces as intermediary components that facilitate efficient data transfer between processing elements and memory. These intermediaries optimize the save/restore process by providing dedicated hardware pathways, reducing the time required for state information transfer compared to general-purpose software access.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If retention flop-based solutions are used for saving PE architecture state information, then the system can maintain state information, but circuit area increases

Engineering Contradiction:

Improvestate information preservationVSAvoidcircuit area

Core Design Contradiction:

ReliabilityVSArea of moving object

Solution Approach 1:

The patent implements a universal save/restore architecture that can serve multiple processing elements through shared routing interfaces and sequencing elements. This multi-functional design eliminates the need for dedicated retention flops at each PE, significantly reducing overall circuit area while maintaining the ability to preserve state information for all PEs.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the save and restore operations into a unified hardware-based system that serves multiple PEs through shared resources. By merging previously separate functions into a common infrastructure, the patent reduces redundant circuitry and minimizes total circuit area required for state preservation.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20260003737A1Hardware based architecture state save and restore for processing elements

Publication Date: 2026.01.01 QUALCOMM INC

AI summary

Certain aspects of the present disclosure provide techniques for hardware-based saving and restoring of architecture state information for processing elements (PEs). According to certain aspects, techniques involve triggering, via one or more circuit elements, saving of architecture state information of at least one processing element (PE) to at least one memory prior to the at least one PE transitioning from a first state to a second state; and triggering, via the one or more circuit elements, restoration of the architecture state information from the at least one memory to the at least one PE prior to the at least one PE transitioning from the second state to the first state.