Peak Detection Circuit With Selective Comparator Activation
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Solution Overview
Problem
Conventional peak detectors and analog-to-digital converters (ADCs) consume excessive power and require significant circuit layout space due to the use of parallel comparators and sample-and-hold circuits, which are not efficiently managed in detecting peak voltage levels.
Innovation Solution
A peak detection/digitization circuit that employs a controller, reference voltage source, digitizer, and decoder, utilizing a comparator and flip-flop configuration that enables selective enabling/disabling of comparators based on the analog input signal, reducing power consumption and eliminating the need for a track-and-hold circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional flash ADC with parallel comparators is used, then peak voltage detection accuracy is achieved, but power consumption becomes excessive
Solution Approach 1:
The parallel bank of comparators is segmented into sequentially activated groups. Instead of enabling all comparators simultaneously, the circuit activates them in stages based on the input signal level, thereby maintaining detection accuracy while significantly reducing power consumption by keeping unused comparators in a low-power state
Solution Approach 2:
The comparator activation state is dynamically adjusted based on the input signal level. The circuit transitions comparators between active and inactive states during operation, optimizing the balance between measurement precision and power consumption according to real-time signal conditions
2Measurement precision
If sample-and-hold circuit is used in peak detector, then peak voltage level detection is achieved, but circuit layout space requirement increases
Solution Approach 1:
The sample-and-hold circuit is extracted and replaced with a direct sampling architecture. The peak detection is achieved by directly comparing the input signal with reference voltages during the sampling phase, eliminating the need for separate sample-and-hold circuitry and thereby reducing the overall circuit layout space
Solution Approach 2:
The sampling and comparison functions are merged into a single operational phase. The circuit performs both sampling and peak detection simultaneously by comparing the instantaneous input signal with the reference voltage ladder, eliminating the need for separate sample-and-hold stages and reducing circuit complexity and area
3Measurement precision
If sample-and-hold circuit is used, then peak detection function is achieved, but power consumption increases
Solution Approach 1:
The power-consuming sample-and-hold circuit is extracted and removed from the architecture. The peak detection function is achieved through direct sequential comparison of the input signal with reference voltages, eliminating the continuous power consumption associated with maintaining hold capacitors and sample circuitry
Solution Approach 2:
The comparison operation is performed periodically in a sequential manner rather than continuously. The circuit activates comparators in discrete steps only when needed for peak detection, thereby reducing average power consumption compared to the continuous operation required by traditional sample-and-hold circuits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves reduced power consumption and smaller layout area by disabling unnecessary comparators and eliminating the track-and-hold circuit, while accurately detecting peak voltage levels with improved efficiency.
Implementation Method 1
A peak detection/digitization circuit that employs a controller, reference voltage source, digitizer, and decoder, utilizing a comparator and flip-flop configuration that enables selective enabling/disabling of comparators based on the analog input signal
Implementation Method 2
utilizing a comparator and flip-flop configuration that enables selective enabling/disabling of comparators based on the analog input signal
Data Source
AI summary
A peak detection/digitization circuit includes a plurality of level detect units, each having a comparator and a flip-flop with a clock input responsive to the output of the comparator. For a detection period, each level detect unit configures a data output signal of the flip-flop to a first data state responsive to a start of the detection period. Further, each level detect unit is configured to enable the comparator responsive to the data output signal having the first data state or a second data state, respectively. While the comparator is enabled during the detection period, the level detect unit configures the data output signal of the flip-flop responsive to a comparison of an input signal to a corresponding reference voltage level by the comparator. The data output signals of the flip-flops of the level detect units at the end of the detection period are used to determine a digital value representative of a peak voltage level of the input signal.