Peak Detector Module for AC-DC Converter

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Solution Overview

Problem

Existing AC-DC converters with secondary side control and synchronous rectifier sense architecture face challenges due to high voltage requirements on the drain node of the synchronous rectifier FET, leading to increased cost, complexity, and size, as well as inaccurate valley detection, which affects efficiency.

Innovation Solution

Implementing a peak-detector module within the secondary side controller that includes a peak comparator and sample and hold circuit to accurately detect peak voltages, allowing for valley switching mode operation and improved sensitivity, thereby reducing the need for high-voltage components and enhancing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If external clamping circuits are used to clip the input to the secondary side controller, then high voltage protection is achieved, but device complexity and number of package pins increase

Engineering Contradiction:
Improvehigh voltage protectionVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the peak detection function from external clamping circuits and integrates it into the secondary side controller IC. The peak detector module is built into the IC, eliminating the need for external clamping components and reducing package pin requirements while maintaining high voltage protection capabilities.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent combines multiple functions (peak detection, voltage clipping, and control) into a single integrated circuit. The peak detector module within the IC merges the previously separate external clamping circuit functionality with the controller, reducing overall device complexity and component count.

Inventive Principle:
Principle #5Merging (Combining)

2Strength

If high voltage FETs are used on the drain node, then voltage handling capability is improved, but cost and device size increase

Engineering Contradiction:
Improvevoltage handling capabilityVSAvoidcost
Core Design Contradiction:
StrengthVSEase of manufacture

Solution Approach 1:

The patent changes the voltage parameter at the drain node by introducing peak detection and voltage clipping functionality. The peak detector module limits the voltage seen by the FET to a safe level, allowing the use of lower voltage-rated, cheaper FETs while maintaining the ability to handle high input voltages through controlled voltage clamping.

Inventive Principle:
Principle #35Parameter changes

3Measurement precision

If peak detection accuracy is improved, then valley switching efficiency is enhanced, but device complexity increases

Engineering Contradiction:
Improvepeak detection accuracyVSAvoiddevice complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements preliminary peak detection and voltage sampling before the main control decision is made. The peak detector module continuously monitors and stores peak voltage information, preparing the data in advance so that accurate valley switching can be performed without requiring complex real-time processing during critical switching events.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11201556B2Accurate peak detection architecture for secondary controlled AC-DC converter
Publication Date: 2021.12.14 INFINEON TECHNOLOGIES AMERICAS CORP
  • US11201556B2 patent drawing
  • US11201556B2 patent drawing
  • US11201556B2 patent drawing

AI summary

An AC-DC converter with synchronous rectifier (SR) architecture and method for operating the same are described. Generally, a secondary side integrated circuit (IC controller of the AC-DC converter includes a peak-detector block coupled to detect peak voltages sensed on a SR-SNS pin. The peak-detector block comprises a peak comparator, a sample-and-hold (S/H) circuit, and a DC offset circuit. The peak comparator is coupled to receive a sinusoidal input from the SR-SNS pin. The S/H circuit is coupled to sample the sinusoidal input and to provide a peak sampled voltage. The DC offset voltage circuit is coupled between the output of the S/H circuit and a reference voltage input of the peak comparator to subtract a DC offset voltage from the peak sampled voltage.