4-Input Peak Detector Circuit for Accurate AGC Peak Tracking
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Solution Overview
Problem
Conventional peak detectors often inaccurately measure signal peaks, leading to over-amplification and potential clipping of received signals due to their limited accuracy and high power consumption, especially when observing signals at or near the 3 dB down point, which can result in increased AGC settling time and signal loss.
Innovation Solution
A 4-input peak detector design that includes an input circuit with five transistors, a bias circuit, and a current mirror, which splits current between transistors based on signal phases, reducing measurement errors and power consumption while maintaining accuracy across a wider tracking bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional peak detectors are used to measure signal peaks, then the device structure is simple, but the measurement accuracy deteriorates at the 3 dB down point leading to over-amplification and clipping
Solution Approach 1:
The peak detector is segmented into five parallel transistor branches, each handling a specific signal phase combination. This segmentation allows the detector to accurately capture peak values across all signal phases, eliminating the 3 dB measurement error that occurs in conventional detectors when signals are at the 3 dB down point.
Solution Approach 2:
Five transistor branches are merged in parallel configuration, each processing different signal phase combinations. The current mirror circuit merges the output currents from all five branches to produce a single accurate peak detection output. This merging approach maintains measurement accuracy while managing circuit complexity through systematic integration.
2Speed
If conventional peak detectors operate with short observation time, then the tracking bandwidth is wide, but the measurement accuracy deteriorates due to higher probability of observing signals at the 3 dB down point
Solution Approach 1:
The five-branch transistor configuration ensures continuous accurate peak detection across all signal phases. By having transistors continuously monitoring different phase combinations, the detector maintains accurate measurement even with short observation times, enabling wide tracking bandwidth without sacrificing precision.
3Measurement precision
If multiple peak detectors are used to improve accuracy, then the measurement precision improves, but the device complexity and power consumption increase
Solution Approach 1:
Five transistor branches are merged in parallel configuration, each processing different signal phase combinations. The current mirror circuit merges the output currents from all five branches to produce a single accurate peak detection output. This merging approach maintains measurement accuracy while managing circuit complexity through systematic integration.
Solution Approach 2:
The five-branch transistor configuration serves multiple functions simultaneously: it detects peak values across all signal phases, eliminates the 3 dB measurement error, and provides accurate output for AGC control. This multi-functionality achieves high measurement precision without requiring multiple separate detector circuits, thereby controlling power consumption.
4Device complexity
If conventional peak detectors are used with quadrature inputs, then the device structure is simple, but the measurement accuracy deteriorates by up to 3 dB below the actual peak level
Solution Approach 1:
The peak detector is segmented into five parallel transistor branches, each handling a specific signal phase combination. This segmentation allows the detector to accurately capture peak values across all signal phases, eliminating the 3 dB measurement error that occurs in conventional detectors when signals are at the 3 dB down point.
Data Source
AI summary
A peak detector including an input circuit with five same-sized transistors, in which four of the input transistors are coupled in parallel between a control node and a bias node and receive a corresponding one of two in-phase signals and two quadrature signals. The fifth transistor is coupled between a current node and the bias node and has its control terminal coupled to an output node. A bias circuit establishes a predetermined bias current that flows through the five input transistors. A current mirror mirrors the current through the fifth transistor from the current terminal into the four parallel-coupled input transistors via the control node. An output circuit charges a peak capacitor based on voltage developed at the control terminal of the fifth transistor. The peak detector is low power and compact and detects the actual peak of the input signal with greater accuracy compared to a conventional peak detector.