Peak Detector Circuit Using Capacitive Sampling
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Solution Overview
Problem
Conventional peak detectors using CMOS transistors in the subthreshold region are impractical for high-speed applications due to high power requirements and large silicon area, and suffer from increasing random and systematic offsets as device sizes decrease.
Innovation Solution
A peak detector circuit that uses a comparator to compare input and output voltages, incrementally adjusts the output voltage by transferring charge between capacitors, and employs self-calibrated digital gates and analog passive devices, operating transistors as switches outside the subthreshold region to minimize power and silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CMOS transistors are operated in the subthreshold region to achieve exponential voltage-to-current characteristic, then the peak detector can rectify the signal, but the power requirements and transistor sizes become large making it impractical for high speed applications
Solution Approach 1:
The patent changes the operating parameters of the CMOS transistors from subthreshold region to above-threshold region. This parameter change allows the transistors to operate as efficient switches with lower power consumption and smaller device sizes while maintaining the peak detection function through a different mechanism (capacitive sampling and hold rather than exponential rectification).
Solution Approach 2:
The patent replaces the exponential rectification mechanism (which requires subthreshold transistor operation) with a capacitive switching mechanism. The peak detector uses switches to sample the input signal onto a capacitor during the positive half-cycle and holds the voltage during the negative half-cycle, eliminating the need for subthreshold operation and its associated power penalties.
2Reliability
If CMOS transistors are operated in the subthreshold region, then the desired exponential behavior is achieved, but the transistor sizes required become large
Solution Approach 1:
The patent changes the operating parameters from subthreshold to above-threshold region, allowing the use of minimum-size transistors as switches. This dramatically reduces the transistor area while maintaining functionality through capacitive sampling rather than exponential current-voltage characteristics.
3Area of moving object
If smaller devices are used to implement peak detectors, then the silicon area is reduced, but random and systematic offsets become worse
Solution Approach 1:
The patent employs self-calibration techniques where the peak detector circuit automatically compensates for its own offsets. The circuit includes calibration logic that detects and corrects systematic offsets in the switches and capacitors, allowing the use of small devices without suffering from degraded offset accuracy.
Solution Approach 2:
The patent incorporates feedback mechanisms through calibration circuits that monitor and adjust for offsets in real-time. This feedback approach allows small devices to be used while maintaining high precision by continuously compensating for offset errors that would otherwise accumulate.
Data Source
AI summary
A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.