PEC Biasing for LEDs Using Isolated Metal Pattern
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Solution Overview
Problem
The existing method of using interconnecting metal on a submount wafer for biasing during photo-electrochemical etching of LEDs leads to exposed traces after sawing, reducing creepage distance, forming leakage paths, and requiring an additional process step for testing, which limits series connections and interconnection of mini-LEDs.
Innovation Solution
A metal pattern is formed on the submount wafer proximate to the N-metal, electrically isolated from the LEDs, which is grounded during PEC etching, using the low resistivity of the KOH solution to bias the N-type layers, allowing for efficient etching and testing without affecting the LEDs' operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interconnecting metal is used on the submount wafer for biasing during PEC etching, then the exposed N-type LED layer can be electrically biased, but the traces are exposed on the sidewalls after sawing, reducing creepage distance and forming leakage paths
Solution Approach 1:
The patent introduces an intermediary metal pattern that is electrically isolated from the LED leads during normal operation but becomes electrically connected to the N-type layer through the conductive KOH solution during PEC etching. This intermediary pattern serves as a mediator that provides biasing during etching without creating leakage paths after sawing, as it is removed or isolated in the final product.
Solution Approach 2:
The patent changes the electrical state of the metal pattern based on the processing stage: during PEC etching, the metal pattern is electrically connected to ground through the conductive KOH solution to provide biasing; after etching and sawing, the metal pattern is electrically isolated from the LED leads to prevent leakage paths. This parameter change in electrical connectivity resolves the contradiction between needing biasing and preventing leakage.
2Productivity
If interconnecting metal is used for biasing, then PEC etching can be performed, but an additional process step is required to cut the metal before testing LED strings
Solution Approach 1:
The patent performs the biasing function in advance during the PEC etching process using the metal pattern that is removed or isolated before final assembly. This preliminary action eliminates the need for additional metal cutting steps before testing, as the biasing function is already accomplished during etching and the metal pattern does not interfere with subsequent testing or operation.
3Reliability
If interconnecting metal is used for biasing, then N-type layers can be biased during PEC etching, but the maximum number of LEDs in series is limited due to reduced creepage distance
Solution Approach 1:
The metal pattern acts as an intermediary that provides electrical connection during the etching process through the conductive KOH solution, but is removed or isolated before final assembly. This allows unlimited series connections to be formed after sawing without the creepage distance limitations that would exist if permanent interconnecting metal traces were present on the sidewalls.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables simultaneous etching of multiple LEDs on a wafer, allows for testing of LED strings, and prevents leakage paths, while maintaining the integrity of the LEDs' operation after singulation, and can be applied to various types of LEDs beyond GaN.
Implementation Method 1
the relatively low resistivity of the KOH solution (e.g., 0.016 ohms·m) effectively shorts the metal pattern to the N-metal for biasing the N-type layers of all the LEDs to ground
Implementation Method 2
Exposure to the UV light generates electron-hole pairs in the semiconductor layer
Implementation Method 3
The holes migrate to the surface of the GaN layer under the influence of the electric field
Data Source
Figure 1~2
Figure 3~4
Figure 5~6B
AI summary
Each LED in an array of LEDs mounted on a submount wafer has at least a first semiconductor layer exposed and connected to a first electrode of each LED. The submount wafer has a first metal portion bonded to the first electrode of each LED for providing an energization current to each LED. The submount wafer also has a second metal portion running along and proximate to the first metal portion but not electrically connected to the first metal portion. The second metal portion may be interdigitated with the first metal portion. The second metal portion is connected to a bias voltage. When the wafer is immersed in an electrically conductive solution for electrochemical (EC) etching of the exposed first semiconductor layer, the solution electrically connects the second metal portion to the first metal portion for biasing the first semiconductor layer during the EC etching.