PECVD Overlay Improvement via Thermal Stress Correction
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Solution Overview
Problem
In semiconductor manufacturing, localized deformation of substrates due to film stress and topography variations between layers leads to overlay errors, causing misalignment and irregularities in device features, which complicates the production of smaller feature size semiconductor devices.
Innovation Solution
A method involving heating substrates in each chamber using thermal energy, measuring local stress patterns, determining sensitivity values, and applying correction factors to adjust thermal energy and match stress patterns between chambers, ensuring uniformity and improving lithographic overlay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple overlying layers are formed on the substrate, then device complexity and functionality are improved, but film stress and topography variations cause localized substrate deformation leading to overlay errors
Solution Approach 1:
The patent applies preliminary action by performing stress measurement and thermal energy adjustment on substrates before subsequent lithographic processing steps. By measuring local stress patterns and adjusting thermal energy in advance, the method compensates for stress-induced deformations before they affect overlay alignment, preventing rather than correcting alignment issues during manufacturing
Solution Approach 2:
The patent utilizes parameter changes by adjusting thermal energy parameters applied to substrates in different chambers based on measured stress patterns. By varying thermal energy parameters and determining sensitivity values, the system compensates for stress-induced deformations, transforming the physical state of the substrate to achieve uniform stress patterns across chambers
2Manufacturing precision
If thermal energy is applied to substrates in different chambers, then stress patterns can be adjusted, but chamber-to-chamber variability in thermal response creates overlay errors
Solution Approach 1:
The patent applies local quality by measuring and adjusting stress patterns at specific locations on substrates rather than treating the entire substrate uniformly. By determining local stress patterns and applying location-specific thermal energy corrections, the system addresses chamber-to-chamber variability with localized precision, allowing each chamber to be optimized for its specific stress characteristics
Solution Approach 2:
The patent implements feedback by measuring local stress patterns in each chamber and using these measurements to adjust thermal energy parameters for subsequent substrates. The system determines sensitivity values based on measured stress responses and applies correction factors in a closed-loop manner, continuously refining thermal energy application to compensate for chamber-specific variations
3Productivity
If feature sizes are reduced to increase device density, then productivity is improved, but localized substrate deformation has a more dramatic effect on alignment precision
Solution Approach 1:
The patent applies preliminary action by compensating for stress-induced deformations before high-precision lithographic steps are performed. By measuring stress patterns and adjusting thermal energy in advance, the system ensures substrates are in an optimal stress state before smaller feature size patterning, preventing deformation from affecting critical alignment precision required for high-density devices
Solution Approach 2:
The patent utilizes parameter changes by adjusting thermal energy parameters based on measured stress patterns to minimize substrate deformation. By optimizing thermal energy parameters and determining sensitivity values, the system reduces stress-induced variations that would otherwise have magnified effects on alignment precision when manufacturing smaller feature size devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively corrects localized substrate deformations, ensuring precise alignment and uniformity between layers, thereby enhancing the reliability and accuracy of semiconductor device fabrication.
Implementation Method 1
heating a substrate in each chamber using thermal energy
Data Source
AI summary
The present disclosure generally relates to a method for performing semiconductor device fabrication, and more particularly, to improvements in lithographic overlay techniques. The method for improved overlay includes depositing a material on a substrate, heating a substrate in a chamber using thermal energy, measuring a local stress pattern of each substrate, wherein measuring the local stress pattern measures an amount of change in a depth of the deposited material on the substrate, plotting a plurality of points on a k map to determine a local stress pattern of the substrate, adjusting the thermal energy applied to the points on the k map, determining a sensitivity value for each of the points on the k map, and applying a correction factor to the applied thermal energy to adjust the local stress pattern.