PECVD Oxide Layer for GaN Wafer Planarity
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Solution Overview
Problem
Semiconductor wafers, particularly GaN-on-sapphire wafers, often exhibit surface non-planarity due to warp and bow, which impedes processing yields and bonding properties, necessitating an inexpensive method to enhance flatness.
Innovation Solution
A method involving the engineered deposition of a compressive dielectric thin film layer, such as PECVD silicon oxide, on the second surface of semiconductor wafers to induce strain-modifying forces, reducing warp and bow through lattice mismatch and thermal expansion mismatch, and subsequent fusion bonding to form a high-quality bonded wafer assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semiconductor wafers are used as-is from fabrication, then production cost is low, but surface planarity is poor with warp and bow exceeding 80 μm
Solution Approach 1:
The patent applies preliminary action by depositing the dielectric layer on the wafer backside before wafer bonding or photolithography processes. This pre-planarization step addresses the surface non-planarity issue in advance, enabling subsequent processes to proceed without requiring additional planarization steps or causing defects from warp and bow.
Solution Approach 2:
The patent changes physical parameters by controlling the dielectric layer thickness (typically 1-10 μm) and material properties to generate specific stress magnitudes. By adjusting these parameters, the stress applied to the wafer can be tuned to achieve the desired planarity correction, reducing warp and bow to below 80 μm without excessive complexity.
2Manufacturing precision
If wafer warp and bow are reduced through traditional mechanical methods, then surface flatness improves, but processing time and cost increase significantly
Solution Approach 1:
The patent replaces mechanical planarization methods (such as grinding, polishing, or pressing) with a stress-based approach using deposited dielectric layers. This substitution eliminates time-consuming mechanical processing steps while achieving the same or better planarity results through controlled stress application during thin film deposition.
Solution Approach 2:
By changing from mechanical force application to controlled stress through thin film deposition parameters (thickness, material composition, deposition conditions), the process achieves rapid planarity improvement without the time penalties of mechanical methods.
3Manufacturing precision
If a thick dielectric layer is deposited to reduce warp, then planarity improves, but subsequent bonding and processing become difficult due to excessive surface profile deviation
Solution Approach 1:
The patent optimizes the dielectric layer thickness parameter to achieve the right balance. By controlling thickness within specific ranges (1-10 μm typically), sufficient stress is generated to reduce warp and bow below 80 μm while avoiding excessive thickness that would create surface profile deviations complicating subsequent bonding operations.
Solution Approach 2:
The patent applies partial action by using just enough dielectric material to achieve the required planarity correction without over-correcting. This controlled partial application ensures warp reduction to acceptable levels while maintaining surface profile compatibility with subsequent bonding and processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method significantly reduces warp and bow, improving wafer planarity, enhancing yields in photolithography and bonding steps, with average reductions of 6.3 μm warp and 3.4 μm bow per 1 μm of oxide deposited, and achieving high-quality bonded semiconductor wafer assemblies.
Implementation Method 1
A thin film layer having a predetermined thickness, pattern or coefficient of thermal expansion (“CTE”) is deposited on the second surface to induce a predetermined strain-modifying compressive or tensile force or a compressive and tensile force
Implementation Method 2
A thin film layer having a predetermined thickness, pattern or coefficient of thermal expansion (“CTE”) is deposited on the second surface to induce a predetermined strain-modifying compressive or tensile force
Data Source
AI summary
A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.