Semiconductor Assembly Pedestal Bonding Wire Stability
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Solution Overview
Problem
The increasing power density of semiconductor chips leads to heat concentration on small footprint areas, causing mechanical instability issues with bonding wire loops and potential electrical spark-overs due to long distances traversed on substrate conductors, especially when different semiconductor chips with varying sizes are used on the same substrate.
Innovation Solution
A semiconductor assembly that includes a pedestal with a higher breakdown voltage than the semiconductor chip, allowing the bonding wire to be bonded at two locations, one on the chip electrode and one on the pedestal electrode, which provides improved mechanical stability and electrical insulation by keeping the bonding wire distant from conductors, thereby preventing spark-overs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the semiconductor chip is mounted on a large-area substrate conductor to act as heat spreader, then heat dissipation is improved, but the bonding wire has to traverse a long distance in a large loop which adversely affects the mechanical stability of the bonding wire loop
Solution Approach 1:
A pedestal structure is introduced as an intermediary element between the semiconductor chip and the substrate conductor. The pedestal provides a localized bonding area close to the chip, allowing the bonding wire to form a short loop while the pedestal itself thermally couples to the large-area substrate conductor for heat dissipation. This mediator resolves the contradiction by separating the thermal management function (large-area substrate) from the electrical connection function (short bonding wire loop).
2Adaptability or versatility
If different semiconductor chips with varying sizes are used on the same substrate, then adaptability is improved, but free sections of substrate conductor surface remain causing bonding wire loops to traverse long distances
Solution Approach 1:
The pedestal provides a localized bonding area with specific electrical and thermal properties, tailored to each chip's requirements. Each chip-pedestal combination can be optimized independently, allowing different chip sizes to be mounted on the same substrate without compromising bonding wire stability. The pedestal's local presence ensures that bonding wires always have a short path regardless of chip size variations.
3Reliability
If the bonding wire traverses a long distance on the substrate conductor, then electrical connection is maintained, but the risk of electrical spark-over increases
Solution Approach 1:
The pedestal acts as an intermediary that provides a dedicated bonding location close to the semiconductor chip. This eliminates the need for the bonding wire to traverse long distances across the substrate conductor surface, thereby reducing the risk of electrical spark-over while maintaining reliable electrical connection. The pedestal serves as a protected intermediate structure that isolates the bonding wire from the substrate conductor.
4Power
If more semiconductor chips are attached to increase current rating, then power handling capability is improved, but more free section of substrate conductor surface remains causing bonding wire instability
Solution Approach 1:
The pedestal structure serves multiple functions: it provides a bonding location for the semiconductor chip, establishes electrical connection to the substrate conductor, and enables thermal coupling. This universal structure can be used with any number of chips, allowing current rating to be increased by adding parallel chip-pedestal combinations without compromising bonding wire stability, as each chip has its own dedicated pedestal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances the mechanical stability of bonding wire loops and prevents electrical spark-overs by ensuring the bonding wire is insulated from conductors, allowing the semiconductor assembly to handle higher voltages and currents without breakdown, thus improving the reliability and efficiency of semiconductor assemblies.
Implementation Method 1
For each polarity of an electrical voltage applied between the first chip electrode and the second chip electrode, the magnitude of a breakdown voltage of the second semiconductor body is greater than the magnitude of a breakdown voltage of the first semiconductor body
Data Source
Figure 1~4
Figure 5~8
AI summary
The semiconductor assembly includes a first semiconductor chip (1), a pedestal (3) and a first bonding wire (5). The first semiconductor chip (1) is disposed on a substrate (2) and includes a first semiconductor body (10), a first chip electrode (11) and a second chip electrode (12). The pedestal (3) is disposed on the substrate (2) and includes a second semiconductor body (30), a first pedestal electrode (31) and a second pedestal electrode (32). The second pedestal electrode (32) is electrically connected to the second chip electrode (12). The first bonding wire (5) is, at a first bonding location (51), bonded to the first chip electrode (11) and, at a second bonding location (52), to the first pedestal electrode (3). The second semiconductor body (30) comprises a series circuit with two diode (s) connected back-to-back between the first pedestal electrode (31) and the second pedestal electrode (32), so that for each polarity of an electrical voltage applied between the first chip electrode (11) and the second chip electrode (12), the magnitude of a breakdown voltage of the second semiconductor body (30) is greater than the magnitude of a breakdown voltage of the first semiconductor body (10).