Pedestal FeRAM Pocket Integration for Logic Height Matching
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Solution Overview
Problem
The integration of ferroelectric random-access memory (FeRAM) devices with logic devices on the same plane is challenging due to the difficulty in etching materials of varying thicknesses, particularly in matching the device thickness with the height constraints of interconnects in adjacent logic regions, which hinders the formation of high-density memory arrays.
Innovation Solution
A pedstal-based pocket integration process is employed, allowing for the decoupling of transition electrode thickness from the insulator layer thickness in the logic region, enabling the tuning of ferroelectric device height while maintaining a fixed insulator layer thickness, and using non-lead based perovskite materials for environmental friendliness and high-density FeRAM device formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used to form FeRAM devices, then the device thickness can be controlled, but it becomes difficult to match the height constraints of interconnects in adjacent logic regions
Solution Approach 1:
The patent divides the FeRAM device structure into distinct segments: a pedestal structure formed in the substrate, a ferroelectric layer deposited on the pedestal, and an electrode structure. This segmentation allows independent control of each component's dimensions, enabling the ferroelectric layer thickness to be optimized for memory performance while the pedestal and electrode structures are adjusted to match logic region interconnect height constraints.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional pedestal-based integration. By forming raised pedestal structures in the substrate and building FeRAM devices vertically on these pedestals, the invention utilizes the vertical dimension to accommodate varying thickness requirements. This dimensional change allows FeRAM devices with thicker ferroelectric layers to coexist with logic region interconnects having strict height constraints.
2Quantity of substance
If high-density FeRAM arrays are formed, then memory capacity increases, but fabrication complexity and cost increase
Solution Approach 1:
The patent employs a universal pedestal formation process that can be applied across the entire wafer surface, creating identical structural foundations for high-density FeRAM arrays. The same deposition and etching processes used for logic region interconnects are adapted to form the pedestal structures, reducing the need for additional specialized fabrication steps and maintaining process compatibility while enabling high-density integration.
Solution Approach 2:
The pedestal structures are formed in advance before the ferroelectric layer deposition. This preliminary action establishes the structural framework and height references early in the fabrication sequence, allowing subsequent layers to be deposited conformally and patterned with simplified processes. The pre-formed pedestals serve as templates that guide the formation of high-density device arrays, reducing overall fabrication complexity.
Data Source
AI summary
A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.