Pedestal-Assisted High-Aspect-Ratio Hole Formation in Semiconductor Devices
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Solution Overview
Problem
The challenge in semiconductor manufacturing is forming high-aspect-ratio holes in interlayer insulating films for connecting upper and lower conductors and capacitors, where the increasing aspect ratio leads to tapering issues, reduced etching rates, and increased contact resistance due to the accumulation of reaction products, making it difficult to maintain precise hole dimensions and capacitor shape.
Innovation Solution
The method involves forming a pedestal within the insulating film, etching to expose the pedestal, and then removing it to create a continuous hole, allowing for the use of non-silicon-containing materials and plasma etching to reduce the burden on the silicon oxide film, thereby maintaining a larger opening area and preventing tapering, and ensuring proper contact and capacitor formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If dry etching is used to form holes in interlayer insulating film, then holes can be formed to connect upper and lower conductors, but the holes exhibit tapering toward the bottom and reduced opening area when aspect ratio increases
Solution Approach 1:
The hole formation process is segmented into two distinct stages: first forming a hole through the upper insulating film to expose the pedestal top surface, then removing the pedestal to complete the hole through the lower insulating film. This segmentation allows each stage to be optimized independently, preventing tapering by controlling the etching process in manageable sections rather than attempting to etch the entire high-aspect-ratio hole in one continuous operation.
Solution Approach 2:
A pedestal structure is formed in advance at the position where the hole will be formed, before the actual hole etching begins. This preliminary action provides a physical reference and support structure that maintains hole geometry during etching, preventing tapering. The pedestal is subsequently removed after serving its geometric control function, leaving a perfectly formed hole with adequate opening area.
2Length of moving object
If hole depth is increased to achieve higher integration, then more conductors can be connected, but etching rate decreases and reaction products accumulate
Solution Approach 1:
The deep hole etching process is divided into two segments: the first segment etches through the upper insulating film to expose the pedestal, and the second segment removes the pedestal to complete the hole. This segmentation reduces the etching burden on silicon oxide by approximately one-third, significantly improving etching rate and preventing reaction product accumulation that would otherwise occur in a single continuous etching operation.
Solution Approach 2:
The etching process parameters are changed between the two stages by using different etching conditions optimized for each segment. The first stage uses parameters optimized for etching through the upper insulating film, while the second stage uses parameters optimized for removing the pedestal material. This parameter optimization maintains high etching rates throughout the process and prevents reaction product accumulation.
3Device complexity
If conventional hole formation method is used, then manufacturing process is simple, but contact resistance increases due to reduced contact area
Solution Approach 1:
A pedestal structure is formed in advance at the position where the hole will be formed, before the actual hole etching begins. This preliminary action provides a physical reference and support structure that maintains hole geometry during etching, preventing tapering. The pedestal is subsequently removed after serving its geometric control function, leaving a perfectly formed hole with adequate opening area.
Solution Approach 2:
The hole formation process is segmented into two distinct stages: first forming a hole through the upper insulating film to expose the pedestal top surface, then removing the pedestal to complete the hole through the lower insulating film. This segmentation allows each stage to be optimized independently, preventing tapering by controlling the etching process in manageable sections rather than attempting to etch the entire high-aspect-ratio hole in one continuous operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces tapering in high-aspect-ratio holes, maintains a larger contact area between plugs and conductors, and allows for the formation of capacitors with favorable characteristics by controlling the hole dimensions and preventing etching stoppages, thus enhancing the integration and performance of semiconductor devices.
Implementation Method 1
The semiconductor devices require a plug to be formed in an interlayer insulating film in order to connect an upper interconnection layer and a lower interconnection layer together. The plug is normally formed by forming a hole in the interlayer insulating film by dry etching
Data Source
AI summary
The present invention provides a method for manufacturing a semiconductor device, including the step of forming a hole penetrating an insulating film over a semiconductor substrate, wherein the step includes the steps of forming a pedestal at a position where a hole to be formed; forming an insulating film to bury the pedestal; forming a first hole in the insulating film so as to expose a top surface of the pedestal; and removing the pedestal to form a second hole continuous with the first hole to form a hole penetrating the insulating film.