Pedestal Pocket Integration for High-Density FeRAM Logic Co-Fabrication
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Solution Overview
Problem
The integration of ferroelectric random-access memory (FeRAM) devices with logic devices on the same plane is challenging due to variations in device thickness and etching difficulties, particularly in achieving a high-density array with height constraints from adjacent logic region interconnects.
Innovation Solution
A multistep subtractive patterning process is employed to decouple the transition electrode thickness from the insulator layer in the logic region, allowing for independent tuning of the ferroelectric device thickness while maintaining a fixed insulator layer thickness, using non-lead-based perovskite materials and high-selectivity etching techniques to form ferroelectric capacitors with hardmask materials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If ferroelectric devices are integrated with logic devices on the same plane, then device density is improved, but manufacturing precision deteriorates due to thickness variations and etching difficulties
Solution Approach 1:
The patent divides the ferroelectric device structure into distinct segments: a bottom electrode, a ferroelectric layer, and a top electrode, with the bottom electrode forming a pedestal structure. This segmentation allows independent control and optimization of each layer's thickness and properties, enabling precise manufacturing despite the complexity of integrating multiple materials with different thicknesses on the same plane as logic interconnects.
Solution Approach 2:
The patent employs parameter changes by adjusting the thickness of the bottom electrode pedestal and the ferroelectric layer independently. The bottom electrode thickness is optimized to provide mechanical support and electrical connection, while the ferroelectric layer thickness is tuned to achieve the desired capacitance and memory performance. This independent parameter control resolves the manufacturing precision challenge by allowing separate optimization of each component's dimensions.
2Quantity of substance
If high-density FeRAM devices are formed, then device density is improved, but device complexity increases due to multiple materials and processing steps
Solution Approach 1:
The bottom electrode serves multiple functions: it acts as the electrical connection to the ferroelectric layer, provides mechanical support as a pedestal structure, and functions as part of the capacitor structure itself. This multi-functionality reduces the need for additional separate components and simplifies the overall device architecture, making high-density integration more manageable despite the presence of multiple materials.
Solution Approach 2:
The patent implements a nested structure where the ferroelectric layer is positioned within the space defined by the bottom electrode pedestal and the top electrode. The top electrode is formed over the ferroelectric layer, creating a nested capacitor structure. This nesting approach efficiently utilizes vertical space to achieve high device density while organizing multiple materials in a compact, manageable configuration.
3Area of stationary object
If ferroelectric devices are integrated adjacent to logic interconnects, then area utilization is improved, but etching difficulty increases due to height constraints
Solution Approach 1:
The patent transitions from a planar integration approach to a three-dimensional structure by forming the bottom electrode as a raised pedestal. This vertical dimension allows the ferroelectric capacitor to be integrated adjacent to logic interconnects on the same plane while maintaining proper height relationships. The pedestal structure elevates the capacitor, creating sufficient clearance for etching processes and allowing adjacent logic interconnects to be formed without height constraint conflicts.
Solution Approach 2:
The bottom electrode pedestal is formed in advance before the ferroelectric layer and top electrode are deposited. This preliminary formation of the pedestal structure establishes the vertical reference and clearance needed for subsequent processing steps. By preparing the supporting structure first, the patent enables easier etching and patterning of adjacent logic interconnects without height constraint issues, as the pedestal already defines the proper elevation level.
Data Source
AI summary
A pocket integration for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.