Penetrable Encapsulation for Stacked IC Packaging

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional integrated circuit packaging systems face challenges such as reduced surface area on printed circuit boards, manufacturing defects, and inefficiencies in stacking multiple semiconductor packages, leading to decreased production yield and increased costs due to issues like mold damage and warpage.

Innovation Solution

A method involving a base package substrate with component and stacking pads, a penetrable encapsulation material to enclose the integrated circuit die, and stacked interconnects adjacent to the encapsulation material, which reduces manufacturing defects and improves yield by preventing flash and overspill, while also enhancing rigidity with a stiffener that can act as an electromagnetic interference shield.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If multiple semiconductor packages are stacked vertically to reduce surface area, then area utilization improves, but manufacturing defects increase due to mold damage and warpage

Engineering Contradiction:

Improvesurface areaVSAvoidmanufacturing defects

Core Design Contradiction:

Area of moving objectVSManufacturing precision

Solution Approach 1:

The patent divides the packaging system into separate functional layers: a base package substrate with component pads, a penetrable encapsulation material layer, and stacked interconnects. This segmentation allows each layer to be optimized independently, reducing manufacturing defects while maintaining vertical stacking for area reduction.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The penetrable encapsulation material serves as an intermediary between the base integrated circuit die and the stacked interconnects. This intermediary layer prevents direct contact between the die and potential contaminants, reducing manufacturing defects while enabling the vertical stacking architecture.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If conventional molding process is used to enclose the die, then protection is provided, but leakage or flash contaminates electrical contacts

Engineering Contradiction:

ImproveprotectionVSAvoidleakage or flash contamination

Core Design Contradiction:

Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The patent employs a penetrable encapsulation material that allows controlled penetration during the stacking process. This porous or penetrable structure enables the encapsulation to protect the die while preventing flash contamination of electrical contacts, as the material can be selectively penetrated only where needed for interconnect formation.

Inventive Principle:

Principle #31Porous materials

Solution Approach 2:

The base integrated circuit die is coupled to the component pads and enclosed with the penetrable encapsulation material before the stacked interconnects are formed. This preliminary encapsulation prevents flash contamination during subsequent manufacturing steps while maintaining protection of the die.

Inventive Principle:

Principle #10Preliminary action

3Length of moving object

If thin mold cap is used to maintain thin package, then package thickness is reduced, but integrated circuit die cracking occurs

Engineering Contradiction:

Improvepackage thicknessVSAvoiddie cracking

Core Design Contradiction:

Length of moving objectVSStrength

Solution Approach 1:

The patent transitions from a conventional thin mold cap structure to a vertical stacking architecture with a penetrable encapsulation material. This dimensional change allows the package to maintain thin profile while providing sufficient structural support through the encapsulation material, preventing die cracking during the stacking process.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

4Quantity of substance

If multiple semiconductor devices are integrated into one package, then capacity increases, but production yield decreases due to single point of failure

Engineering Contradiction:

Improvedevice integrationVSAvoidproduction yield

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The patent segments the integrated circuit system into a base package with one or more dies and separately stackable interconnect layers. This segmentation allows individual devices to be tested and validated independently before stacking, improving production yield while maintaining high device integration capacity in the final assembled package.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS8404518B2Integrated circuit packaging system with package stacking and method of manufacture thereof

Publication Date: 2013.03.26 STATS CHIPPAC LTD

AI summary

A method of manufacture of an integrated circuit packaging system including: fabricating a base package substrate having component pads and stacking pads; coupling a base integrated circuit die to the component pads; forming a penetrable encapsulation material for enclosing the base integrated circuit die and the component pads on the base package substrate; and coupling stacked interconnects on the stacking pads adjacent to and not contacting the penetrable encapsulation material.