Penetrating Electrodes as Alignment Marks for 3D Chip Stacking
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Solution Overview
Problem
The challenge in stacking semiconductor chips with penetrating electrodes is the difficulty in achieving accurate alignment due to the need for different planar shapes of alignment marks, which can lead to distortion and reduced dimensional accuracy, making it hard to recognize positions accurately for efficient chip stacking.
Innovation Solution
The semiconductor device incorporates a configuration where first through-substrate vias serve as alignment marks, with second and third through-substrate vias arranged at specific pitches and connected to conductive patterns, allowing for accurate alignment and electrical connection, and using back-surface bumps for alignment on the interface chip, enabling precise stacking without compromising the formation of original penetrating electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If different planar shapes of alignment marks are used for chip stacking, then alignment can be performed, but dimensional accuracy deteriorates due to distortion and tapered edges
Solution Approach 1:
The patent merges the function of penetrating electrodes with alignment marks by using the same photoresist pattern for both purposes. The penetrating electrodes themselves serve as the alignment marks, eliminating the need for separate alignment mark structures and avoiding the dimensional accuracy problems associated with different-shaped marks.
Solution Approach 2:
The penetrating electrodes are given dual functionality: they serve both as electrical connection elements and as alignment marks for chip stacking. This multi-functionality resolves the contradiction by using the same structure for both alignment and electrical purposes, maintaining dimensional accuracy while enabling alignment.
2Ease of manufacture
If photoresist film thickness is increased to 20 μm for penetrating electrode formation, then electrode formation is enabled, but alignment mark accuracy deteriorates due to tapered edges
Solution Approach 1:
The patent combines the penetrating electrode formation process with alignment mark formation by using the same photoresist pattern and etching process for both. The thick photoresist (20 μm) is used for both purposes simultaneously, and the same pattern geometry is maintained, so the tapered edges affect both functions equally without compromising the electrical connection functionality.
3Quantity of substance
If the number of memory chips stacked is increased, then storage capacity is improved, but device complexity increases due to more wires needed for connection
Solution Approach 1:
The patent merges multiple functions into the penetrating electrodes: electrical connection between chips, alignment reference for stacking, and positioning reference for bump electrodes. This consolidation eliminates the need for separate wire connections and alignment mark structures, reducing device complexity while enabling increased chip stacking to improve storage capacity.
Solution Approach 2:
The penetrating electrodes serve multiple functions simultaneously: they provide electrical connectivity, serve as alignment marks for the recognition camera, and define bump electrode positions. This multi-functionality reduces the overall device complexity by eliminating separate structures for each function, allowing more chips to be stacked without proportionally increasing complexity.
Data Source
AI summary
Disclosed herein is a device that includes: a semiconductor substrate; plurality of first through-substrate vias each penetrating through the semiconductor substrate, a plurality of second through-substrate vias each penetrating through the semiconductor substrate, an insulating film formed over the semiconductor substrate, the insulating film including a first opening and a plurality of second openings, the first opening being located over the first through-substrate vias, and each of the second openings being located over a corresponding one of the second through-substrate vias.