Penetrating Electrode Configuration for Stacked Semiconductor Bonding
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Solution Overview
Problem
The challenge in stacking semiconductor memory chips with penetrating electrodes is the uneven bonding strength due to warping, which can lead to electrical short-circuits and reduced reliability, especially when accurate positioning is required for the bump electrodes to connect effectively.
Innovation Solution
The semiconductor device incorporates a configuration with penetrating electrodes arranged in specific patterns, including dummy electrodes, to enhance mechanical strength and bonding reliability by increasing the formation density of penetrating electrodes, particularly at the peripheries, and using a combination of top-surface and back-surface bumps for secure connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semiconductor chips are stacked with accurate positioning to ensure bump electrode contact, then connection precision is improved, but bonding strength becomes uneven due to warping
Solution Approach 1:
The patent applies local quality by providing penetrating electrodes at different locations with different connection configurations. Specifically, penetrating electrodes at peripheral positions are connected to both upper and lower bump electrodes, while those at central positions connect only to lower bump electrodes. This local differentiation compensates for warping effects at different chip regions, ensuring uniform bonding strength across the entire chip stack despite positioning variations.
Solution Approach 2:
The patent implements beforehand cushioning by pre-configuring the penetrating electrode connections to anticipate and compensate for warping effects. The dual-connection design at peripheral positions creates a mechanical cushioning effect that absorbs positioning errors and warping-induced stress before they can cause bonding failures, thereby maintaining reliable connections despite manufacturing variations.
2Productivity
If the number of memory chips stacked is increased, then storage capacity is improved, but the number of electrodes connected to package substrate must increase
Solution Approach 1:
The patent applies universality by designing penetrating electrodes that serve multiple functions simultaneously. Each penetrating electrode acts as both a mechanical support structure and an electrical connection pathway. The electrodes at peripheral positions provide both structural reinforcement against warping and electrical connectivity, while central electrodes provide electrical connections, allowing the same basic structure to fulfill multiple roles and enabling higher chip stacking without proportionally increasing electrode complexity.
3Reliability
If bump electrodes are made to contact accurately for reliable connections, then bonding strength is improved, but positioning requirements become more stringent
Solution Approach 1:
The patent applies local quality by differentiating the connection configuration of penetrating electrodes based on their location. Peripheral penetrating electrodes connect to both upper and lower bump electrodes, providing enhanced mechanical support and tolerance for positioning variations at the chip edges. Central penetrating electrodes connect only to lower bump electrodes, simplifying the connection requirement in the chip center region. This location-based differentiation reduces overall positioning stringency while maintaining bonding reliability.
Data Source
AI summary
Disclosed herein is a device including a first semiconductor chip having a first internal circuit formed in a first substrate, and a plurality of penetrating electrodes each penetrating through the first semiconductor substrate. The plurality of penetrating electrodes includes first, second, third and fourth penetrating electrodes arranged along a first line. The first and second penetrating electrodes are in a floating state without being electrically connected to the first internal circuit. The third penetrating electrode is electrically connected to a first power supply line that conveys a first power supply potential to the first internal circuit. The fourth penetrating electrode is electrically connected to a second power supply line that conveys a second power supply potential to the first internal circuit. The third and fourth penetrating electrodes are arranged between the first penetrating electrode and the second penetrating electrode.