Pentacene OFET Buffer Layer for Lower P/E Voltage and Better Retention
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Solution Overview
Problem
Pentacene organic field-effect transistors (OFETs) using polymer films as charge trapping dielectrics face issues with high operation voltage, low programming/erasing speed, poor endurance, and retention degradation due to positively charged defects at the pentacene/polymer interface, which impede hole transfer and result in high working voltages.
Innovation Solution
Incorporating an n-type semiconductor buffer layer or interlayer between the polymer charge-trapping dielectric and pentacene, which reduces the height of the hole-barrier by electrostatic induction, thereby decreasing programming/erasing gate voltages and improving the endurance and retention characteristics of pentacene OFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polymer films are used as charge trapping dielectric in pentacene OFETs, then charge storage capability is improved, but operation voltage increases and programming/erasing speed decreases
Solution Approach 1:
An n-type semiconductor interlayer is introduced between the polymer charge trapping dielectric and the pentacene semiconductor layer. This interlayer acts as an intermediary that reduces the hole-barrier height at the interface through electrostatic induction, facilitating easier hole transfer while maintaining the charge storage capability of the polymer layer.
Solution Approach 2:
The invention changes the electrical parameters at the interface by introducing the n-type semiconductor interlayer with different carrier concentration and mobility characteristics. This modifies the electrostatic field distribution and reduces the effective barrier height, enabling lower operation voltages without sacrificing charge storage performance.
2Reliability
If polymer films are used as charge trapping dielectric in pentacene OFETs, then charge storage capability is improved, but programming/erasing speed decreases
Solution Approach 1:
The n-type semiconductor interlayer serves as a mediator that accelerates the hole transfer process between the polymer dielectric and pentacene layer by reducing the barrier height, thereby improving programming and erasing speeds while preserving the charge storage function.
Solution Approach 2:
By modifying the interface electrical parameters through the n-type interlayer, the charge transfer kinetics are enhanced, resulting in faster programming and erasing operations without compromising the reliability of charge storage.
3Reliability
If positively charged defects exist at pentacene/polymer interface, then charge trapping is enhanced, but hole transfer is impeded and device stability deteriorates
Solution Approach 1:
The n-type semiconductor interlayer acts as a buffer that mitigates the harmful effects of positively charged defects at the interface. It facilitates charge transfer while protecting the pentacene layer from direct interaction with defect-induced electric fields, thereby improving device stability and endurance.
Solution Approach 2:
The invention converts the harmful positive charge barrier into a beneficial structure by introducing the n-type interlayer that can be electrostatically induced to create a favorable electric field profile, turning the interface defect problem into an opportunity for optimized charge management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The introduction of an n-type semiconductor buffer or interlayer effectively reduces the hole-barrier height, decreases programming/erasing voltages, and enhances the performance of pentacene OFETs by improving field-effect mobility and stability, making them more suitable for practical applications.
Implementation Method 1
Incorporating an n-type semiconductor buffer layer or interlayer between the polymer charge-trapping dielectric and pentacene, which reduces the height of the hole-barrier by electrostatic induction
Data Source
AI summary
A method for enhancing the performance of pentacene organic field-effect transistor (OFET): an n-type semiconductor thin film was set as a buffer layer between pentacene and polymer electret in the OFET with the structure of gate-electrode/insulating layer/polymer/pentacene/source (drain) electrode. The thickness of n-type organic buffer layer is 1˜100 nm. The induced electrons at the interface lead to the reduction of the height of the hole-barrier formed at the interface, thus effectively reducing the programming/erasing (P/E) gate voltages of pentacene OFET. The widened distribution region of positive space charges caused by ionized donors in n-type organic buffer layer effectively restricts the back-transfer of holes from polymer to pentacene, thus improving the performance of pentacene OFET, such as the P/E speeds, P/E endurance and retention characteristics.