Per-bit De-skew Mechanism for Memory Interface Controllers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
DDR SDRAM controllers face challenges with timing skew between strobe and data lines due to static and dynamic variations, leading to memory errors, which existing delay locked loops (DLLs) fail to fully address, especially for large static variations on individual bits or bytes.
Innovation Solution
A memory controller with adjustable delay circuits and control logic that determines and applies per-bit delays to data and strobe lines during read and write operations, using training processes to optimize delay settings for each bit, effectively de-skewing signals and reducing timing skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If delay locked loops (DLLs) are used to compensate for timing skew, then phase alignment between strobe and data lines is improved, but large static variations on individual bits or bytes cannot be fully de-skewed
Solution Approach 1:
The patent divides the delay compensation function into separate per-bit delay elements, where each data bit has its own adjustable delay circuit. This segmentation allows independent adjustment of delay for each bit line, enabling precise de-skewing of large static variations that affect individual bits differently, overcoming the limitation of DLLs that apply uniform phase adjustment to all bits.
Solution Approach 2:
The patent implements local delay adjustment by providing customized delay compensation for each individual bit or byte lane. Control logic determines optimal delay values specifically for each bit based on its timing characteristics, allowing localized precision in timing alignment that addresses the non-uniform static variations across different signal lines.
2Reliability
If per-bit adjustable delay circuits are implemented, then timing skew between data and strobe lines is significantly reduced, but device complexity increases
Solution Approach 1:
The patent implements dynamic delay adjustment through control logic that automatically determines optimal delay values for each bit during initialization or training phases. The delay elements are programmable rather than fixed, allowing the system to adapt to actual timing measurements and optimize performance without requiring complex hardwired delay networks for every possible timing scenario.
Solution Approach 2:
The control logic performs self-calibration by measuring actual timing skew between data and strobe lines and automatically configuring the delay elements to compensate for measured variations. This self-adjusting mechanism eliminates the need for external manual calibration or overly complex control circuits, as the system configures itself based on observed timing characteristics.
Data Source
AI summary
A memory controller may implement variable delay elements, on a per-bit basis, in both the read and write paths. The memory controller may include multiple adjustable delay circuits associated with data lines and a strobe line, each of the adjustable delay circuits inserting an adjustable amount of delay into a signal destined to or received from one of the data lines or the strobe line. The memory controller may additionally include control logic to determine the delay amount for each of the adjustable delay circuits, the delay amount being determined to reduce static skew between each of the data lines and the strobe line.