Per-Block Well Biasing for Integrated Circuit Power Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In deep sub-micron VLSI chip manufacturing, die-to-die and intra-die variations cause significant degradation in chip performance due to power and timing constraints, leading to yield loss, as transistors operating near the slow or fast end of the process range affect frequency and power consumption, respectively, and prior methods of per-chip supply voltage and well bias adjustment are insufficient to meet power and speed constraints.
Innovation Solution
The implementation of per-block well bias adjustment and per-chip supply voltage adjustment, utilizing charge pumps to provide individual well biases and adjustable supply voltages to operational blocks, with storage devices to hold bias settings, allowing for characterization of speed as a function of supply voltage and well bias to optimize block performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If per-chip supply voltage adjustment is used, then power consumption can be controlled, but it is impossible to bring a chip within power and speed constraints due to intra-die variations
Solution Approach 1:
The patent divides the chip into multiple operational blocks, each with its own charge pump for well bias adjustment. This segmentation allows independent control of well bias for each block, enabling fine-grained optimization of both power and speed for blocks with different process variations, thereby meeting both power and speed constraints that cannot be achieved with coarse per-chip supply voltage adjustment alone.
Solution Approach 2:
The patent applies local well bias adjustment to specific operational blocks based on their individual performance characteristics. Blocks operating near the slow end receive forward well bias to speed them up, while blocks near the fast end receive reverse well bias to reduce leakage. This localized approach optimizes power and speed for each block according to its specific needs, resolving the contradiction between power control and constraint fulfillment.
2Speed
If transistors operate near the fast end of the process range, then speed is improved, but power consumption increases due to leakage current
Solution Approach 1:
The patent changes the well bias parameter for operational blocks based on their process variation characteristics. For blocks operating near the fast end, reverse well bias is applied to increase the potential well depth, thereby reducing leakage current. For blocks near the slow end, forward well bias is applied to decrease well depth and reduce resistance, improving speed. This dynamic parameter adjustment resolves the trade-off between speed and leakage power.
3Use of energy by stationary object
If transistors operate near the slow end of the process range, then power consumption is reduced, but frequency performance suffers
Solution Approach 1:
The patent applies forward well bias to operational blocks operating near the slow end of the process range. This forward bias decreases the well depth and reduces the resistance of the well, thereby improving the speed and frequency performance of these slow blocks. By selectively applying well bias based on block performance, the patent improves frequency without significantly increasing overall power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved chip performance by equalizing operating frequencies across blocks and reducing power consumption, thereby increasing yield and meeting target specifications by selectively applying well biases and adjusting supply voltages based on characterized relationships.
Implementation Method 1
each operational block comprising an operational circuit and a charge pump to provide well biases to the operational circuit
Data Source
AI summary
An integrated circuit includes a substrate, a storage device formed in the substrate to hold bias settings, and operational blocks formed in the substrate, each operational block including an operational circuit and a charge pump to provide well bias voltages to the operational circuit in response to one or more of the bias settings. A method for testing an integrated circuit having two or more operational blocks includes: (a) determining a maximum operating speed of each of the blocks at a minimum supply voltage; (b) selecting a block that has a slow operating speed; (c) selecting a well bias to speed up the selected block; (d) selecting a supply voltage to meet a target operating frequency at the selected well bias and measuring power; (e) repeating acts (b)-(d) while the measured power is less than a baseline power; and (f) saving the selected well bias and supply voltage settings for operation of the integrated circuit.