Per-Channel Memory Frequency Optimization

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Solution Overview

Problem

As memory channel speeds increase and the number of channels supported by processors grows, maintaining a common memory channel speed across a system becomes costly due to signal degradations like crosstalk and circuit path discontinuities, especially with the proliferation of different types of DIMMs with varying maximum speeds.

Innovation Solution

The system employs a BIOS/UEFI that trains each memory channel to its highest attainable speed based on the performance level of its Dual In-Line Memory Modules (DIMMs) and allocates memory resources accordingly, ensuring optimal performance by setting channel speeds to the slowest DIMM speed and allowing for interleaved channels to operate at the same speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If a common memory channel speed is maintained across all channels, then system stability is improved, but signal degradation from crosstalk and circuit path discontinuities worsens

Engineering Contradiction:
Improvesystem stabilityVSAvoidsignal degradation
Core Design Contradiction:
Stability of the object's compositionVSObject-affected harmful factors

Solution Approach 1:

The patent segments the memory system into independent per-channel frequency domains, allowing each channel to be trained and operated at its own optimal speed rather than forcing a common frequency across all channels. This segmentation enables channels with different signal quality characteristics to operate independently without mutual interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by allowing each memory channel to have its own frequency characteristics tailored to its specific signal quality. Channels with better signal quality can operate at higher frequencies while channels affected by crosstalk or discontinuities operate at lower frequencies, optimizing performance locally for each channel's conditions.

Inventive Principle:
Principle #3Local quality

2Productivity

If memory channel speeds are increased to improve performance, then data transfer efficiency is improved, but the cost of maintaining high-speed operations across multiple channels increases

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidcost of maintaining high-speed operations
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent introduces dynamic frequency adjustment where each channel's operating frequency is determined by its individual training results rather than being fixed at a common high speed. This dynamic approach allows the system to adapt each channel's speed to its actual performance capabilities, avoiding the energy waste of forcing all channels to operate at uniformly high speeds.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If different DIMM types with varying maximum speeds are supported, then adaptability is improved, but maintaining a common channel speed reduces overall system performance

Engineering Contradiction:
Improvesupport for different DIMM typesVSAvoidoverall system performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent enables each channel to be trained and operate at a frequency appropriate to its specific DIMM type and signal quality, rather than forcing all channels to use the same frequency. This allows the system to fully utilize the capabilities of different DIMM types while maintaining optimal performance across the board.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11341037B2System and method for providing per channel frequency optimization in a double data rate memory system
Publication Date: 2022.05.24 DELL PROD LP
  • US11341037B2 patent drawing
  • US11341037B2 patent drawing
  • US11341037B2 patent drawing

AI summary

An information handling system includes a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system, and a second DIMM on a second memory channel of the information handling system. A processor trains the first memory channel to a first speed based upon a first performance level of the first DIMM, trains the second memory channel to a second speed based upon a second performance level of the second DIMM, and allocates a portion of the first DIMM to the application based upon the first speed.