Per-Die ECC Layout for High-Density SSD Throughput Bottlenecks
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Solution Overview
Problem
High-density solid state drives face challenges in extending lifespan and enhancing throughput due to increased raw error rates and congestion caused by a single shared error correction coding (ECC) codec in the controller, particularly with high-density NAND flash memory like QLC NAND, which results in decreased performance and Quality of Service instability.
Innovation Solution
Implementing an ECC codec module on each NAND die to distribute error correction tasks and moving erasure coding to the controller, while offloading other operations like wear-leveling and garbage collection to the host, thereby reducing congestion and enhancing self-correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single ECC codec is shared across multiple NAND channels in high-density SSDs, then device complexity is reduced, but congestion and bottleneck occur resulting in decreased throughput and performance
Solution Approach 1:
The patent divides the single shared ECC codec into multiple separate ECC codecs, with each NAND channel having its own dedicated ECC codec. This segmentation eliminates the congestion and bottleneck that occurred when a single ECC codec served multiple channels, thereby improving throughput and performance while maintaining manageable device complexity through modular architecture.
2Quantity of substance
If high-density NAND flash (e.g., QLC NAND) is used to increase capacity and reduce cost, then storage capacity increases, but raw error rate increases resulting in decreased reliability and lifespan
Solution Approach 1:
The patent changes the ECC codec parameters and algorithms to be optimized for high-density NAND flash characteristics. By adjusting the error correction capabilities and adapting the decoding parameters specifically for QLC NAND's higher error rates, the system maintains reliability while utilizing the high capacity benefits of dense storage media.
3Productivity
If the number of NAND channels increases to enhance throughput, then data transfer capacity increases, but the burden on the shared ECC codec increases resulting in increased latency and decreased Quality of Service stability
Solution Approach 1:
The patent assigns dedicated ECC codecs to each NAND channel, eliminating the queuing and contention that occurred with shared ECC resources. This allows each channel to process error correction independently and simultaneously, reducing decoding latency and improving Quality of Service stability while maintaining high data transfer capacity across multiple channels.
Data Source
AI summary
One embodiment facilitates data placement in a storage device. During operation, the system receives a request indicating first data to be written to a non-volatile memory which includes a plurality of dies, wherein a plurality of error correction code (ECC) codec modules reside on the non-volatile memory. The system receives, by a first codec module residing on a first die, the first data. The system encodes, by the first codec module operating on the first die, the first data based on an error correction code (ECC) to obtain first ECC-encoded data which includes a first set of ECC parity bits. The system writes the first ECC-encoded data to the first die.