Per-Die Memory Cell Read Write Assist Configuration
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Solution Overview
Problem
Memory cell dies in manufacturing exhibit variations leading to unacceptable functionality during read or write operations, with existing solutions like read assist reducing switching speed and write assist increasing power consumption, necessitating either lower production yield or universal enablement of assist functionalities.
Innovation Solution
The implementation of read assist and write assist enabling units, such as fuses or switches, that selectively reduce word line voltage and apply negative charges to bit lines, respectively, on a per-die basis, based on performance testing to optimize functionality without universal enablement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read assist is enabled to reduce read disturb, then read operation reliability is improved, but switching speed deteriorates
Solution Approach 1:
The patent applies local quality by selectively enabling read assist functionality only in specific memory cell dies that exhibit read disturb issues, rather than uniformly across all dies. This is achieved through per-die configuration mechanisms that allow the memory controller to identify and apply read assist voltage adjustments only where threshold voltage shifts cause read errors, thereby maintaining high switching speed in dies that do not require assist while improving reliability only where needed.
2Productivity
If write assist is enabled to pass quality control tests, then manufacturing yield is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by selectively enabling write assist functionality only in memory cell dies that fail quality control tests during manufacturing, rather than uniformly across all dies. Through per-die configuration and testing mechanisms, the system identifies specific dies requiring write assist to pass quality control, applying the assist functionality only to those dies while leaving other dies in their normal low-power state, thereby improving yield without unnecessarily increasing power consumption across the entire memory device.
3Productivity
If universal read assist is applied to all memory cell dies, then production yield is improved, but switching speed of all dies deteriorates
Solution Approach 1:
The patent resolves this contradiction by implementing selective read assist enabling at the per-die level rather than universal application. The memory controller tests each memory cell die individually and enables read assist functionality only in dies that exhibit read disturb characteristics, allowing the majority of dies that perform adequately to operate at full switching speed while still achieving high production yield by salvaging only the problematic dies.
Solution Approach 2:
The patent applies dynamics by making the read assist configuration adjustable and reconfigurable based on actual die performance characteristics. The system allows dynamic enabling or disabling of read assist functionality for each die based on test results and operational requirements, rather than applying a static universal configuration, thereby optimizing the balance between yield and performance.
4Productivity
If universal write assist is applied to all memory cell dies, then production yield is improved, but power consumption of all dies increases
Solution Approach 1:
The patent resolves this contradiction by implementing selective write assist enabling at the per-die level rather than universal application. Through individual die testing and configuration, the system identifies only those dies that require write assist to pass quality control tests, enabling the functionality locally in those specific dies while leaving all other dies in their normal low-power operational state, thereby achieving high yield without unnecessary power consumption penalties.
Data Source
AI summary
A semiconductor device includes at least one memory cell die. The at least one memory cell die includes a data storage unit. The at least one memory cell die includes at least one read assist enabling unit electrically connected to the data storage unit. The at least one read assist enabling unit configured to lower a voltage of a word line. The memory cell die also includes at least one write assist enabling unit electrically connected to the data storage unit. The at least one write assist enabling unit configured to supply a negative voltage to at least one of a bit line or a bit line bar.